> On 29 Nov, 2018, at 10:19 am, Mikael Abrahamsson <swm...@swm.pp.se> wrote: > >> I'd say the important bits are only slightly harder than doing the same with >> fq_codel. > > Ok, FQ_CODEL is way off to get implemented in HW. I haven't heard anyone even > discussing it. Have you (or anyone else) heard differently?
I haven't heard of anyone with a specific project to do so, no. But there are basically three components to implement: 1: Codel AQM. This shouldn't be too difficult. 2: Hashing flows into separate queues. I think this is doable if you accept simplified memory management (eg. assuming every packet is a full MTU for allocation purposes) and accept limited/no support for encapsulated protocols (which simplifies locating the elements of the 5-tuple for hashing). 3: Dequeuing packets from queues following DRR++ rules. I think this is also doable, since it basically means managing some linked lists. It should be entirely feasible to prototype this at GigE speeds using existing FPGA hardware. Development can then continue from there. Overall, it's well within the capabilities of any competent HW vendor, so long as they're genuinely interested. - Jonathan Morton _______________________________________________ Bloat mailing list Bloat@lists.bufferbloat.net https://lists.bufferbloat.net/listinfo/bloat
