https://sourceware.org/bugzilla/show_bug.cgi?id=23956
Bug ID: 23956
Summary: RISC-V 4-operand add doesn't check for %tprel_add
Product: binutils
Version: 2.31
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: luismarques at lowrisc dot org
Target Milestone: ---
In RISC-V assembly, there's a fictitious 4-operand ADD that's used to add a
TP-relative relocation. It's usually used like "add a0,a0,tp,%tprel_add(sym)",
but binutils allows a plain 0 as the 4th operand:
$ cat test.s
add a0, a0, tp, 0
$ riscv32-unknown-elf-as test.s
$
Is this just loose error checking, or is it actually needed in some cases?
There's a patch for TLS support in LLVM that requires the presence of
%tprel_add in the 4-operand add. It's important, then, to clarify if the "add
a0,a0,tp,0" should be accepted or not.
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