https://sourceware.org/bugzilla/show_bug.cgi?id=23212
--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@sourceware.org>: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6456d318aaa7ea35511dad1f2facf0fb984972e5 commit 6456d318aaa7ea35511dad1f2facf0fb984972e5 Author: Tamar Christina <tamar.christ...@arm.com> Date: Thu Feb 7 16:55:23 2019 +0000 AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns. -- You are receiving this mail because: You are on the CC list for the bug. _______________________________________________ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
