https://sourceware.org/bugzilla/show_bug.cgi?id=33893
H.J. Lu <hjl.tools at gmail dot com> changed:
What |Removed |Added
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Last reconfirmed| |2026-03-16
Status|UNCONFIRMED |WAITING
CC| |hjl.tools at gmail dot com
Ever confirmed|0 |1
--- Comment #8 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Craaijo, Jos from comment #0)
> The instruction 66F30FD6E4 is decoded incorrectly by libopcodes. It is
> decoded as:
>
> movq2dq %xmm4,%xmm4
>
> but it should be decoded as:
>
> movq2dq %mm4,%xmm4
>
> Note the register difference in the first operand.
>
> I suspect the 66 prefix is somehow given priority over the F2/F3 prefixes,
> as this decoding would be correct if the instruction was 660FD6E4. When both
> an F2/F3 and a 66 prefix are present, priority should be given to the F2/F3
> prefixes. I have checked this behavior against both Intel and AMD CPUs, as
> well as Capstone, XED and Zydis. Unfortunately, I could not find a
What do Intel/AMD CPUs do?
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