https://sourceware.org/bugzilla/show_bug.cgi?id=34248
Bug ID: 34248
Summary: [RISC-V] RISC-V shared preemptible ADD/SUB wrong
success
Product: binutils
Version: 2.45
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: ld
Assignee: unassigned at sourceware dot org
Reporter: l784896635 at gmail dot com
Target Milestone: ---
Created attachment 16757
--> https://sourceware.org/bugzilla/attachment.cgi?id=16757&action=edit
Reduced testcase
I reduced this to the attached RISC-V testcase and can reproduce it 3/3 times.
Observed: GNU ld.bfd 2.45 links the RV32 and RV64 shared objects successfully
from both GNU-as and LLVM-MC objects, exports default-visible `w1` and `w2` in
`.dynsym`, emits no dynamic relocations, and writes the fixed local value `4`
into `.rodata` slots of widths 64/32/16/8.
Expected: Link a RISC-V shared object containing naturally generated
fixed-width `R_RISCV_ADD64/SUB64`, `R_RISCV_ADD32/SUB32`,
`R_RISCV_ADD16/SUB16`, and `R_RISCV_ADD8/SUB8` relocation pairs for `w2 - w1`
in SHF_ALLOC `.rodata`, where `w1` and `w2` are default-visible DSO function
definitions.
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