Re: Tier 1 SMP Code Review: glibc Signal, RPC, and Threading Subsystems

[Samuel Thibault]

Hello,

Samuel Thibault, le dim. 08 mars 2026 03:15:26 +0100, a ecrit:
> #### P-3: `pthread_once` uses plain load/store with fences (LOW on x86)
> 
> **File**: `sysdeps/htl/pt-once.c:37-53`
> 
> The double-checked locking pattern uses `atomic_full_barrier()` + plain
> load/store rather than C11 atomics. Correct on x86; formally undefined
> behavior in C11 due to data race on non-atomic accesses.

Could you ask Claude whether it believes the code below is correct?

Not tying the memory barrier to the __run store/load indeed looked
incorrect to me for proper synchronization.

Samuel


int
__pthread_once (pthread_once_t *once_control, void (*init_routine) (void))
{
  ASSERT_TYPE_SIZE (pthread_once_t, __SIZEOF_PTHREAD_ONCE_T);

  if (atomic_load_acquire (&once_control->__run) == 0)
    {
      __pthread_spin_wait (&once_control->__lock);

      if (once_control->__run == 0)
        {
          pthread_cleanup_push (clear_once_control, once_control);
          init_routine ();
          pthread_cleanup_pop (0);

          atomic_store_release (&once_control->__run, 1);
        }

      __pthread_spin_unlock (&once_control->__lock);
    }

  return 0;
}