On Wed, Jun 08, 2022 at 11:42:21PM +0100, Chris Narkiewicz wrote:
> On Wed, Jun 08, 2022 at 09:56:09PM +1000, Jonathan Gray wrote:
> > some older snapshots can be found at
> > https://ftp.hostserver.de/archive/
>
> Thanks.
>
> I did a bisect and here is the result:
>
> Works:
> https://ftp.hostserver.de/archive/2022-05-25-0105/snapshots/amd64/install71.img
>
> Broken:
> https://ftp.hostserver.de/archive/2022-05-26-0105/snapshots/amd64/install71.img
>
> Some something changes between 25 and 26 of may that broke X11 on intel.
>
> I don't understand the release cycle well enough to map exact commit
> to the build, but I hope it will be easy to narrow things down.
Can you try this diff against -current which reverts some drm commits
from that timeframe?
97efc481178 drm/i915/dmc: Add MMIO range restrictions
d509a14a9b2 Revert "drm/i915/opregion: check port number bounds for SWSCI
display power state"
diff --git sys/dev/pci/drm/i915/display/intel_dmc.c
sys/dev/pci/drm/i915/display/intel_dmc.c
index da3c7e53b8b..b2fc8882de4 100644
--- sys/dev/pci/drm/i915/display/intel_dmc.c
+++ sys/dev/pci/drm/i915/display/intel_dmc.c
@@ -375,44 +375,6 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
}
}
-static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
- const u32 *mmioaddr, u32 mmio_count,
- int header_ver, u8 dmc_id)
-{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
- u32 start_range, end_range;
- int i;
-
- if (dmc_id >= DMC_FW_MAX) {
- drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
- return false;
- }
-
- if (header_ver == 1) {
- start_range = DMC_MMIO_START_RANGE;
- end_range = DMC_MMIO_END_RANGE;
- } else if (dmc_id == DMC_FW_MAIN) {
- start_range = TGL_MAIN_MMIO_START;
- end_range = TGL_MAIN_MMIO_END;
- } else if (DISPLAY_VER(i915) >= 13) {
- start_range = ADLP_PIPE_MMIO_START;
- end_range = ADLP_PIPE_MMIO_END;
- } else if (DISPLAY_VER(i915) >= 12) {
- start_range = TGL_PIPE_MMIO_START(dmc_id);
- end_range = TGL_PIPE_MMIO_END(dmc_id);
- } else {
- drm_warn(&i915->drm, "Unknown mmio range for sanity check");
- return false;
- }
-
- for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
- return false;
- }
-
- return true;
-}
-
static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, u8 dmc_id)
@@ -482,12 +444,6 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return 0;
}
- if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
- dmc_header->header_ver, dmc_id)) {
- drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
- return 0;
- }
-
for (i = 0; i < mmio_count; i++) {
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
dmc_info->mmiodata[i] = mmiodata[i];
diff --git sys/dev/pci/drm/i915/display/intel_opregion.c
sys/dev/pci/drm/i915/display/intel_opregion.c
index df469af1667..610a1e40d81 100644
--- sys/dev/pci/drm/i915/display/intel_opregion.c
+++ sys/dev/pci/drm/i915/display/intel_opregion.c
@@ -376,6 +376,21 @@ int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder,
return -EINVAL;
}
+ /*
+ * The port numbering and mapping here is bizarre. The now-obsolete
+ * swsci spec supports ports numbered [0..4]. Port E is handled as a
+ * special case, but port F and beyond are not. The functionality is
+ * supposed to be obsolete for new platforms. Just bail out if the port
+ * number is out of bounds after mapping.
+ */
+ if (port > 4) {
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] port %c (index %u) out of bounds
for display power state notification\n",
+ intel_encoder->base.base.id,
intel_encoder->base.name,
+ port_name(intel_encoder->port), port);
+ return -EINVAL;
+ }
+
if (!enable)
parm |= 4 << 8;
diff --git sys/dev/pci/drm/i915/i915_reg.h sys/dev/pci/drm/i915/i915_reg.h
index 3c70aa5229e..bb64e7baa1c 100644
--- sys/dev/pci/drm/i915/i915_reg.h
+++ sys/dev/pci/drm/i915/i915_reg.h
@@ -7818,22 +7818,6 @@ enum {
/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
#define DMC_MMIO_START_RANGE 0x80000
#define DMC_MMIO_END_RANGE 0x8FFFF
-#define DMC_V1_MMIO_START_RANGE 0x80000
-#define TGL_MAIN_MMIO_START 0x8F000
-#define TGL_MAIN_MMIO_END 0x8FFFF
-#define _TGL_PIPEA_MMIO_START 0x92000
-#define _TGL_PIPEA_MMIO_END 0x93FFF
-#define _TGL_PIPEB_MMIO_START 0x96000
-#define _TGL_PIPEB_MMIO_END 0x97FFF
-#define ADLP_PIPE_MMIO_START 0x5F000
-#define ADLP_PIPE_MMIO_END 0x5FFFF
-
-#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1),
_TGL_PIPEA_MMIO_START,\
- _TGL_PIPEB_MMIO_START)
-
-#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1),
_TGL_PIPEA_MMIO_END,\
- _TGL_PIPEB_MMIO_END)
-
#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
