#3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA -------------------------------------------+--------------------- Reporter: pragnesh | Owner: (none) Type: task | Status: new Priority: normal | Milestone: 5.1 Component: arch/riscv | Version: 5 Severity: normal | Resolution: Keywords: #RISCV, #FREEDOME310, #ARTYA7 | Blocked By: Blocking: | -------------------------------------------+---------------------
Comment (by Sebastian Huber <sebastian.huber@…>): In [changeset:"ae5546704d15fa87a111760d777e95321143c199/rtems" ae554670/rtems]: {{{ #!CommitTicketReference repository="rtems" revision="ae5546704d15fa87a111760d777e95321143c199" bsp/riscv: Fix format and warnings Update #3785. }}} -- Ticket URL: <http://devel.rtems.org/ticket/3785#comment:7> RTEMS Project <http://www.rtems.org/> RTEMS Project
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