Pavel Pisa commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/312#note_115167 From **PolarFire SoC MSS Technical Reference Manual** 3.1.2.5 Data Cache (Ask a Question) The U54 dCache has an 8-way set-associative 32 KB write-back, VIPT data cache memory with a line size of 64 bytes. Access latency is two clock cycles for words and double-words, and three clock cycles for smaller quantities. Misaligned accesses are not supported in hardware and result in a trap. dCache is kept coherent with a directory-based cache coherence manager, which resides in the L2 cache. So it seems that misaligned accesses are not supported in hardware and has to be emulate by software. So it seems that for RISC-V ABI compliance (misaligned accesses are allowed in software), there is mandatory to install emulation handler when RTEMS is running in M-mode and no SBI is present. The HSS integrates OpenSBI for this purpose and relevant code is available at https://github.com/polarfire-soc/hart-software-services/blob/master/thirdparty/opensbi/lib/sbi/sbi_misaligned_ldst.c https://github.com/polarfire-soc/hart-software-services/blob/master/thirdparty/opensbi/lib/sbi/sbi_trap.c#L294 -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/312#note_115167 You're receiving this email because of your account on gitlab.rtems.org.
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