Le Quoc Viet Pham commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_147754 Hi, I was looking through the file `bsps/riscv/esp32/include/c3/chip_definitions.h` and compare it to the ESP32C3 datasheet (https://documentation.espressif.com/esp32-c3_technical_reference_manual_en.pdf#usbserialjtag). I might need some clarification: * In chapter 8, page 202, it says "The ESP32-C3 has 62 peripheral interrupt sources". Why in the file, the **RISCV_MAXIMUM_EXTERNAL_INTERRUPTS** is defined as **63** instead of **62**? * I saw a comment: `/* * These interrupts aren't used on ESP32-C-series chips as they are * single-core, but they're useful for generating software interrupts. */` So I'm assuming that from bit 50 to bit 59, these interrupts aren't be used because C3 is a single core. But in the datasheet, i couldn't find anything telling me that these bits are using for dual-core or anything related. * `/* ESP32-C3 ROM function addresses */ #define UART_TX_ONE_CHAR_ADDR ((void *)(uintptr_t)0x40000068) #define UART_RX_ONE_CHAR_ADDR ((void *)(uintptr_t)0x40000070) #define UART_TX_FLUSH_ADDR ((void *)(uintptr_t)0x40000080) #define GPIO_OUTPUT_SET_ADDR ((void *)(uintptr_t)0x400005b0)` In page 92, Figure 3.2-1. based 0x4000000 is pointing to the ROM0 using instruction bus. But I cannot find anything related to bit 68,70,80, ... * In the future, I just need to adjust these numbers (bits and address) based on the datasheet of C5 and C6 right? I would not need to add anything else maybe? Thank you!!! -- View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5527#note_147754 You're receiving this email because of your account on gitlab.rtems.org.
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