Sam Price commented: https://gitlab.rtems.org/rtems/tools/rtems-source-builder/-/work_items/169#note_153528 >From a brief glance Xilinx GCC is carrying 4 patches that are not in the >mailine gcc for the 32 bit version. - [8 Stage pipeline model](https://github.com/thesamprice/gcc/commit/89a6cc55a I am not sure if we are compiled for this. - [Disable -fivopts](github.com/thesamprice/gcc/commit/05227fb9d) Could be disabled by `-fno-ivopts` in the bsp opts. Would need performance results before / after. Minor ones - [bitfield opt](github.com/thesamprice/gcc/commit/c3220f3f8) - [zero_extend opt](github.com/thesamprice/gcc/commit/ac1e8cde5) These look like optimization changes to me. I am guessing going from gcc4 to 15.2 will probably be more of a speedup than these optimizations. I have a modified version of qemu that I can track basic cycle counts. - Xilinx 4, 13 versions. - Mainline 15, and 17 {width=900 height=554} Arith stood out to me, I ran the optimizations without the -fno-ivopts flag. Diffing the assembly between the two, 15/17 is not making use of the delay slot. I will post -no-ivopts performance tomorrow. Compiling withh -no-ivopts did put the delay slot into the assembly. I expect better -- View it on GitLab: https://gitlab.rtems.org/rtems/tools/rtems-source-builder/-/work_items/169#note_153528 You're receiving this email because of your account on gitlab.rtems.org. Unsubscribe from this thread: https://gitlab.rtems.org/-/sent_notifications/4-5nwbxmui8856en00zj6e7oytr-e/unsubscribe | Manage all notifications: https://gitlab.rtems.org/-/profile/notifications | Help: https://gitlab.rtems.org/help
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