Greetings all. I've just finished a revamped 10Ge (v2) controller for Virtex-5 devices, which has been integrated into the mlib_10_1 build (ROACH target only).
The old 10Ge controller ran into timing trouble at roughly 200 MHz on RX and 260 MHz on TX, also it used a ton of BRAMS (13). These two show-stopper issues warranted a rewrite of the core. The new core has the following features: * Application interface tested at 333MHz (RX+TX) * Reduced Block-RAM utilization: Typical utilization 7, without CPU interface 3, worst-case 9 (if application clock < 156.25) * Receive CRC using Virtex-5 CRC hard-macros * Written entirely in Verilog with a fairly comprehensive simulation test-harness targeted for the Icarus Verilog simulator - Note: with this core the maximum TX frame size is 8k The application interface has changed a little. Documentation will be up on the wiki soon at http://casper.berkeley.edu/wiki/Ten_GbE_v2 The software interface remains the same. The core is still very green and equires a bit more testing. It would be great if some CASPER folk with ROACHs would get their hands dirty. Cheers, David -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: [email protected] Web: www.ska.ac.za
