The problem of trying to program the FPGA is kernel related, not filesystem. You will need to reflash your onboard FLASH. We have had no problems with this at KAT, but in the interests of making certain, we're recompiling everything and testing from scratch. Wan, we will give you step-by-step instructions for updating your board later today.
Billy, please remove that roach.tar.bz2 file from the CASPER webserver. It was a temporary arrangement to help you get Berkeley's ROACH boards up. The authoritative source for ROACH-related software will be the CASPER SVN.
Jason On 14 May 2009, at 11:01, William Mallard wrote:
Hi Wan, I will assume that by "ROACH core" you mean "ROACH root filesystem" (or "rootfs" for short). As it says on the wiki, you should really just download our pre-built root filesystem. From the wiki:A pre-built root filesystem is now available. Unless you have good reason, you should probably use that. $ wget http://casper.berkeley.edu/software/roach/roach.tar.bz2Or rather, this is what the wiki said when i wrote my last email. Last week, it looks like Jason changed the URL to a non-existent location in our Subversion repository. I just reverted that wiki page and notified Jason. Sorry for the confusion. You should just download the pre-built root filesystem from here: http://casper.berkeley.edu/software/roach/roach.tar.bz2 I've updated the wiki with instructions on how to expand the size of this pre-built rootfs. Billy [email protected] wrote:Hi: I could build a ROACH core finally today. The size is much bigger 1GB than the core I downloaded from wiki trunk 250MB. But the core could not boot and an error imformation is kept showing: Can't open /dev/ttyS0: No such file or directory process '/sbin/getty 115200 ttyS0' (pid 324) exited. Scheduling for restart. Can't open /dev/ttyS0: No such file or directory process '/sbin/getty 115200 ttyS0' (pid 325) exited. Scheduling for restart. Can't open /dev/ttyS0: No such file or directory It seems the serial port is not initialized correctly. Anybody has any idea? And anybody could tell me a good start point? What's the revision number? Thanks Wan -----Original Message----- From: William Mallard [mailto:[email protected]] Sent: Monday, 4 May 2009 2:30 PM To: Cheng, Wan (ATNF, Marsfield) Cc: [email protected] Subject: Re: [casper] FPGA could not be configured Hi Wan, We've had Debian running on ROACH for about a month here in Berkeley. As Henry said in his last email:The other possibility is that the kernel you have on the board is outdated and doesn't yet support the differences in the bitstream it has to download to the FPGA. You may need to recompile the kernel you have for your board. Instructions for obtaining and building the kernel can be found here: http://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACHI had to work with the South Africans for a week to get it running, but i documented the process thoroughly on the wiki. See the page that Henry referenced above for instructions. I encountered the same "SelectMap - Done pin has not been asserted" problem that you are describing. The problem should be fixed after SVN revision 1812. We are able to run bof files on the SX95 boards. Billy [email protected] wrote:Hi Henry: I try to download a bitstream which is created with pof file at same time with JTAG. It is successful. Have you made any progress with Roach Debian core? Can you run pof file with that core? Thanks. Wan Attached Jtag download log: // *** BATCH CMD : Program -p 1 Maximum TCK operating frequency for this device chain: 33000000. Validating chain... Boundary-scan chain validated successfully. PROGRESS_START - Starting Operation. 1: Device Temperature: Current Reading: 27.24 C, Min. Reading: 27.24 C, Max. Reading: 28.23 C 1: VCCINT Supply: Current Reading: 0.996 V, Min. Reading: 0.996 V, Max. Reading: 0.999 V 1: VCCAUX Supply: Current Reading: 2.511 V, Min. Reading: 2.508 V, Max. Reading: 2.514 V '1': Programming device... Match_cycle = NoWait. Match cycle: NoWait done. '1': Reading status register contents... CRC error : 0 Decryptor security set : 0 DCM locked : 1 DCI matched : 1 End of startup signal from Startup block : 1 status of GTS_CFG_B : 1 status of GWE : 1 status of GHIGH : 1 value of MODE pin M0 : 1 value of MODE pin M1 : 1 Value of MODE pin M2 : 0 Internal signal indicates when housecleaning is completed: 1 Value driver in from INIT pad : 1 Internal signal indicates that chip is configured : 1 Value of DONE pin : 1 Indicates when ID value written does not match chip ID: 0 Decryptor error Signal : 0 System Monitor Over-Temperature Alarm : 0 startup_state[18] CFG startup state machine : 0 startup_state[19] CFG startup state machine : 0 startup_state[20] CFG startup state machine : 1 E-fuse program voltage available : 0 SPI Flash Type[22] Select : 0 SPI Flash Type[23] Select : 0 SPI Flash Type[24] Select : 0 CFG bus width auto detection result : 1 CFG bus width auto detection result : 0 Reserved : 0 BPI address wrap around error : 0 IPROG pulsed : 0 read back crc error : 0 Indicates that efuse logic is busy : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 1111 1101 1110 0000 1000 0100 0000 INFO:iMPACT:579 - '1': Completed downloading bit file to device. Match_cycle = NoWait. Match cycle: NoWait INFO:iMPACT - '1': Checking done pin....done. '1': Programmed successfully. PROGRESS_END - End Operation. Elapsed time = 13 sec. -----Original Message----- From: Henry Chen [mailto:[email protected]] Sent: Friday, 1 May 2009 2:58 AM To: Cheng, Wan (ATNF, Marsfield) Cc: [email protected]; Beresford, Ron (ATNF, Marsfield); [email protected] Subject: Re: FPGA could not be configured Hi Wan, Again, I ask you to send all questions to the mailing list. Not only do you access a greater pool of expertise in that manner, but also at least you are able to contribute to the collaboration by bringing problems and their potential solutions to light. The most probable issue is that your bitstream is incompatible with the board. Are you compiling your design for the ROACH SX95T platform? ROACH prototypes were built with LX110T devices, whereas the shipping production versions have SX95T. The option is available from the XSG Core Config block platform dropdown menu. The other possibility is that the kernel you have on the board is outdated and doesn't yet support the differences in the bitstream it has to download to the FPGA. You may need to recompile the kernel you have for your board. Instructions for obtaining and building the kernel can be found here: http://casper.berkeley.edu/wiki/Setting_Up_BORPH_on_ROACH -Henry [email protected] wrote:Anybody has some idea? Thanks Wan ------------------------------------------------------------------------ *From:* Cheng, Wan (ATNF, Marsfield) *Sent:* Wednesday, 29 April 2009 11:55 AM *To:* '[email protected]' *Cc:* '[email protected]'; Beresford, Ron (ATNF, Marsfield) *Subject:* FPGA could not be configured Hi Henry: I can boot the Debian core from external USB stick. But it seems that the bitstream could not be loaded correctly. When I execute the bof file, I receive a input/output error. Please see the following dmesg error information. It seems that the FPGA configure done pin could not been asserted. That means the FPGA configuration is failed. bkexecd: configuring fpga 0 bkexecd: got region bkexecd: got ioreg sys_board_id, mode=3, loc=0, len=2 bkexecd: got ioreg sys_rev, mode=3, loc=4, len=4 bkexecd: got ioreg sys_rev_rcs, mode=3, loc=8, len=4 bkexecd: got ioreg sys_scratchpad, mode=3, loc=10, len=4 bkexecd: got ioreg sys_monitor, mode=3, loc=14, len=8 bkexecd: got ioreg sys_irq_controller, mode=3, loc=1c, len=10 bkexecd: got ioreg iadc_controller, mode=3, loc=20000, len=10000 bkexecd: got ioreg snap_addr, mode=1, loc=1000000, len=100 bkexecd: got ioreg snap_bram, mode=3, loc=1000100, len=40000 bkexecd: got ioreg snap_ctrl, mode=3, loc=1080000, len=100 bkexecd: got ioreg software_register, mode=3, loc=1080100, len=100 bkexecd: getting hwrops from class 3 bkexecd: Before we configure, let's clear our bookkeeping first hwrtype_roach: Configuring ROACH fpga 0 from (offset 4451, len 4464512) of adctest1.bof hwrtype_roach: SelectMap - Done pin has not been asserted borph: kill fpga process at region 0x0 hwrtype_roach: Unconfigure ROACH fpga 0 borph: check hcptr binfmt_bof: hw load error Thanks Wan
