Hi Randy, If you open the system.twx file in the Xilinx timing analyzer tool, it will show you which paths are causing the problem. One thing I would suggest is adding delays with register retiming enabled on all of the BRAM signals. Thus a delay of say 2 on DIN, WE, and ADDR. This might help if it is indeed the BRAM that is the problem. I am more suspicious that the vector accumulator is being optimized out when you terminate the inputs, and that the timing problems are coming from inside there. Can you attach a zipped version of the model file? The version you send got copied as plaintext. Glenn
On 4/11/08, Randy McCullough <[email protected]> wrote: > All, > > Even though we've used BRAMS successfully in quite a few designs > running at different clock rates (including 200MHz), we seem to be > having a snag while attempting to marry some BRAMS with Glen > Jones' Vector Accumulator design. > > Attached, you'll find a brief explanation of what we're attempting > to do along with the report generated during our failed build attempts > which consistently report timing problems related to dcm_3. Also, I've > attached the model in question; which was extracted from a much larger > target design. > > Any insight you might be able to share would be greatly appreciated!!! > > Thanks, > > Randy > > Randy L. McCullough, Digital Group Leader > National Radio Astronomy Observatory > P.O. 2 > Route 28/92 > Green Bank, WV 24944 > > Phone: (304)-456-2214 > Fax: (304)-345-2200 > Email: [email protected] > > > > 11-ARP-08 > > All, > > The following report was generated during an attempt to build > a subset of a current design we're working on. The overall system > design calls for using an externally generated clock (from an iBOB) > driving the Userclk input of our bee2; then selecting Bee2_userclk2X > 200MHz. This exerpt (and it's parent design) build perfectly at 100Mhz; > but consistently fail to build at 200MHz; reporting timing constraint > errors having to do with dcm_3. > > If I remove the BRAMS and simply terminate the otherwise unused > outputs, the design builds perfectly at 200MHz; but if I connect > only one BRAM's data input (while terminating it's ADDRESS and WE > inputs with constants, the whold thing fails to build at 200MHz > with the exact same error messages... > > I've also attached the model file from which this report was generated. > If you drill into the vacc block, you'll see that its output stage is > comprised of four BRAMS which are filled during the 512 clock cycles > during which the vacc's DATA VALID line is high. Following this, a > "negedge" block is used to trigger an external circuit to assume control > of the BRAMS and read out their contents. This all seems to simulate > perfectly and seems to run reliably when built and run at 100MHz. > > Any ideas why this design fails to build at 200MHz??? Unfortunately, > when the build fails, we see no timing report generated; which, of > course, makes analyzing timing errors a bit difficult!!! > > Thanks in advance, > > Randy > > ****************************************************************************** > > >> startup > >> simulink > Warning: The model 'vacc_brams_test' does not have continuous states, hence > using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can > disable this diagnostic by explicitly specifying a discrete solver in the > solver tab of the Configuration Parameters dialog, or setting 'Automatic > solver parameter selection' diagnostic to 'none' in the Diagnostics tab of > the Configuration Parameters dialog. > >> bee_xps > ############################# > ## System Update ## > ############################# > Warning: The model 'vacc_brams_test' does not have continuous states, hence > using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can > disable this diagnostic by explicitly specifying a discrete solver in the > solver tab of the Configuration Parameters dialog, or setting 'Automatic > solver parameter selection' diagnostic to 'none' in the Diagnostics tab of > the Configuration Parameters dialog. > > In gen_xps_files at 145 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > ############################# > ## Block objects creation ## > ############################# > ###################### > ## Checking objects ## > ###################### > Running system generator ... > Warning: The model 'vacc_brams_test' does not have continuous states, hence > using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can > disable this diagnostic by explicitly specifying a discrete solver in the > solver tab of the Configuration Parameters dialog, or setting 'Automatic > solver parameter selection' diagnostic to 'none' in the Diagnostics tab of > the Configuration Parameters dialog. > > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateModel.p>xlGenerateModel > at 169 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModel.p>xlCompileModel > at 27 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModelStruct.p>xlCompileModelStruct > at 2 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileGenerateMdl.p>xlCompileGenerateMdl > at 172 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateButton.p>xlGenerateButton > at 265 > In gen_xps_files at 231 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > Warning: Using a default value of 0.2 for maximum step size. The > simulation step size will be limited to be less than this value. You can > disable this diagnostic by setting 'Automatic solver parameter selection' > diagnostic to 'none' in the Diagnostics page of the configuration parameters > dialog. > > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateModel.p>xlGenerateModel > at 169 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModel.p>xlCompileModel > at 27 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModelStruct.p>xlCompileModelStruct > at 2 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileGenerateMdl.p>xlCompileGenerateMdl > at 172 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateButton.p>xlGenerateButton > at 265 > In gen_xps_files at 231 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > Warning: The model 'vacc_brams_test' does not have continuous states, hence > using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can > disable this diagnostic by explicitly specifying a discrete solver in the > solver tab of the Configuration Parameters dialog, or setting 'Automatic > solver parameter selection' diagnostic to 'none' in the Diagnostics tab of > the Configuration Parameters dialog. > > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateModel.p>xlGenerateModel > at 176 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModel.p>xlCompileModel > at 27 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModelStruct.p>xlCompileModelStruct > at 2 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileGenerateMdl.p>xlCompileGenerateMdl > at 172 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateButton.p>xlGenerateButton > at 265 > In gen_xps_files at 231 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > Warning: The model 'vacc_brams_test' does not have continuous states, hence > using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can > disable this diagnostic by explicitly specifying a discrete solver in the > solver tab of the Configuration Parameters dialog, or setting 'Automatic > solver parameter selection' diagnostic to 'none' in the Diagnostics tab of > the Configuration Parameters dialog. > > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateModel.p>xlGenerateModel > at 340 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModel.p>xlCompileModel > at 27 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileModelStruct.p>xlCompileModelStruct > at 2 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlCompileGenerateMdl.p>xlCompileGenerateMdl > at 172 > In > C:\MATLAB704\toolbox\xilinx\sysgen\bin\xlGenerateButton.p>xlGenerateButton > at 265 > In gen_xps_files at 231 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > XSG generation complete. > ######################### > ## Copying base system ## > ######################### > ######################## > ## Copying custom IPs ## > ######################## > ########################## > ## Creating Simulink IP ## > ########################## > ########################## > ## Creating EDK files ## > ########################## > ######################### > ## Elaborating objects ## > ######################### > ############################## > ## Preparing software files ## > ############################## > ######################### > ## Running EDK backend ## > ######################### > Warning: File > 'C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\implementation\download.bit' > not found. > > In gen_xps_files at 1030 > In bee_xps>run_Callback at 132 > In bee_xps at 64 > > Xilinx Platform Studio > Xilinx EDK 7.1.2 Build EDK_H.12.5.1 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > XPS% Loading xmp file system.xmp > > XPS% Evaluating file run_xps.tcl > *************************************************** > Creating system netlist for hardware specification. > *************************************************** > platgen -p xc2vp70ff1704-7 -lang vhdl -st xst system.mh > > Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > > Command Line: platgen -p xc2vp70ff1704-7 -lang vhdl -st xst system.mhs > > Parse system.mhs ... > > Read MPD definitions ... > Sourcing tcl file > C:/EDK/hw/XilinxProcessorIPLib/pcores/ppc405_v2_00_c/data/ppc405_v2_1_0.tcl > ... > Sourcing tcl file > C:/EDK/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/data/jtagppc_cntlr_v > 2_1_0.tcl ... > Sourcing tcl file > C:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/data/plb_bram_if > _cntlr_v2_1_0.tcl ... > Sourcing tcl file > C:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/data/plb2opb_bridge > _v2_1_0.tcl ... > Sourcing tcl file > C:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/data/plb_v34_v2_1_0.tcl > ... > > Overriding IP level properties ... > dcm_module (dcm_0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0. > mpd:56 - tool overriding c_family value virtex2 to virtex2p > dcm_module (dcm_1) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0. > mpd:56 - tool overriding c_family value virtex2 to virtex2p > dcm_module (dcm_2) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0. > mpd:56 - tool overriding c_family value virtex2 to virtex2p > dcm_module (dcm_3) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0. > mpd:56 - tool overriding c_family value virtex2 to virtex2p > jtagppc_cntlr (jtagppc_0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_00_a\data\jtagppc_cntlr_v > 2_1_0.mpd:33 - tool overriding c_device value X2VP4 to 2vp70 > bram_block (plb_bram_if_cntlr_1_bram) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:39 - tool overriding c_family value virtex2 to virtex2p > bram_block (vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:39 - tool overriding c_family value virtex2 to virtex2p > bram_block (vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:39 - tool overriding c_family value virtex2 to virtex2p > bram_block (vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:39 - tool overriding c_family value virtex2 to virtex2p > bram_block (vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:39 - tool overriding c_family value virtex2 to virtex2p > > Performing IP level DRCs on properties... > > Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC... > Address Map for Processor ppc405_0 > (0xd0000000-0xd0001fff) > vacc_brams_test_vacc_subsys_I_I_0_BRAM > plb->plb2opb_bridge_0->opb0 > (0xd0002000-0xd0003fff) > vacc_brams_test_vacc_subsys_I_I_1_BRAM > plb->plb2opb_bridge_0->opb0 > (0xd0004000-0xd0005fff) > vacc_brams_test_vacc_subsys_I_I_2_BRAM > plb->plb2opb_bridge_0->opb0 > (0xd0006000-0xd0007fff) > vacc_brams_test_vacc_subsys_I_I_3_BRAM > plb->plb2opb_bridge_0->opb0 > (0xd0fffe00-0xd0ffffff) opb_selectmap_fifo_0 plb->plb2opb_bridge_0->opb0 > (0xffff0000-0xffffffff) plb_bram_if_cntlr_1 plb > Address Map for Processor ppc405_1 > > Check platform configuration ... > plb_v34 (plb) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:185 - 2 > master(s) : 2 slave(s) > opb_v20 (opb0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:194 - 1 > master(s) : 5 slave(s) > > Check port drivers... > > Check platform address map ... > > Overriding system level properties ... > bram_block (plb_bram_if_cntlr_1_bram) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:35 - tool overriding c_memsize value 2048 to 65536 > bram_block (plb_bram_if_cntlr_1_bram) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:36 - tool overriding c_port_dwidth value 32 to 64 > bram_block (plb_bram_if_cntlr_1_bram) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:38 - tool overriding c_num_we value 4 to 8 > plb_bram_if_cntlr (plb_bram_if_cntlr_1) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bram_if > _cntlr_v2_1_0.mpd:40 - tool overriding c_num_masters value 8 to 2 > plb_bram_if_cntlr (plb_bram_if_cntlr_1) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b\data\plb_bram_if > _cntlr_v2_1_0.mpd:47 - tool overriding c_plb_mid_width value 3 to 1 > plb2opb_bridge (plb2opb_bridge_0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_bridge > _v2_1_0.mpd:48 - tool overriding c_plb_num_masters value 4 to 2 > plb2opb_bridge (plb2opb_bridge_0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb2opb_bridge_v1_01_a\data\plb2opb_bridge > _v2_1_0.mpd:49 - tool overriding c_plb_mid_width value 4 to 1 > plb_v34 (plb) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mpd:39 > - tool overriding c_plb_num_masters value 4 to 2 > plb_v34 (plb) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mpd:40 > - tool overriding c_plb_num_slaves value 4 to 2 > plb_v34 (plb) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a\data\plb_v34_v2_1_0.mpd:41 > - tool overriding c_plb_mid_width value 2 to 1 > opb_v20 (opb0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36 > - tool overriding c_num_masters value 4 to 1 > opb_v20 (opb0) - > C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:37 > - tool overriding c_num_slaves value 4 to 5 > bram_block (vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:35 - tool overriding c_memsize value 2048 to 8192 > bram_block (vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:35 - tool overriding c_memsize value 2048 to 8192 > bram_block (vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:35 - tool overriding c_memsize value 2048 to 8192 > bram_block (vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk) > - > C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0. > mpd:35 - tool overriding c_memsize value 2048 to 8192 > > Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC... > > Performing System level DRCs on properties... > > Running UPDATE Tcl procedures for OPTION > PLATGEN_SYSLEVEL_UPDATE_PROC... > > Modify defaults ... > > Processing licensed instances ... > Completion time: 0.00 seconds > > Creating hardware output directories ... > > Managing hardware (BBD-specified) netlist files ... > vacc_brams_test (vacc_brams_test_xsg_core_config) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:222 - > Copying > (BBD-specified) netlist files. > opb_selectmap_fifo (opb_selectmap_fifo_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:27 - > Copying (BBD-specified) > netlist files. > > Managing cache ... > > Elaborating instances ... > bram_block (plb_bram_if_cntlr_1_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:155 - > elaborating IP > bram_block (vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk) > - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:263 - > elaborating IP > bram_block (vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk) > - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:293 - > elaborating IP > bram_block (vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk) > - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:323 - > elaborating IP > bram_block (vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk) > - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:353 - > elaborating IP > > Writing HDL for elaborated instances ... > > Inserting wrapper level ... > Completion time: 8.00 seconds > > Constructing platform-level signal connectivity ... > Completion time: 13.00 seconds > > Writing (top-level) BMM ... > Writing BMM - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\implementation\system.bmm > > Writing (top-level and wrappers) HDL ... > > Generating synthesis project file ... > > Running XST synthesis ... > INFO:MDT - The following instances are synthesized with XST. The MPD option > IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST > synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. > opb_selectmap_fifo_0_wrapper (opb_selectmap_fifo_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:27 - > Running XST synthesis > reset_block_wrapper (reset_block) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:39 - > Running XST synthesis > dcm_0_wrapper (dcm_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:55 - > Running XST synthesis > dcm_1_wrapper (dcm_1) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:78 - > Running XST synthesis > dcm_2_wrapper (dcm_2) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:93 - > Running XST synthesis > dcm_3_wrapper (dcm_3) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:111 > - Running XST synthesis > ppc405_0_wrapper (ppc405_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:126 - > Running XST synthesis > ppc405_1_wrapper (ppc405_1) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:142 - > Running XST synthesis > jtagppc_0_wrapper (jtagppc_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:148 - > Running XST synthesis > plb_bram_if_cntlr_1_bram_wrapper > (plb_bram_if_cntlr_1_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:155 - > Running XST synthesis > plb_bram_if_cntlr_1_wrapper (plb_bram_if_cntlr_1) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:161 - > Running XST synthesis > plb2opb_bridge_0_wrapper (plb2opb_bridge_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:172 - > Running XST synthesis > plb_wrapper (plb) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:185 - > Running XST synthesis > opb0_wrapper (opb0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:194 - > Running XST synthesis > diffclk_buf_0_wrapper (diffclk_buf_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:202 - > Running XST synthesis > diffclk_buf_1_wrapper (diffclk_buf_1) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:210 - > Running XST synthesis > vacc_brams_test_xsg_core_config_wrapper > (vacc_brams_test_xsg_core_config) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:222 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_0_bram_ramif_wrapper > (vacc_brams_test_vacc_subsys_i_i_0_bram_ramif) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:251 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk_wrapper > (vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:263 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_0_bram_wrapper > (vacc_brams_test_vacc_subsys_i_i_0_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:270 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_1_bram_ramif_wrapper > (vacc_brams_test_vacc_subsys_i_i_1_bram_ramif) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:281 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk_wrapper > (vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:293 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_1_bram_wrapper > (vacc_brams_test_vacc_subsys_i_i_1_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:300 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_2_bram_ramif_wrapper > (vacc_brams_test_vacc_subsys_i_i_2_bram_ramif) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:311 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk_wrapper > (vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:323 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_2_bram_wrapper > (vacc_brams_test_vacc_subsys_i_i_2_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:330 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_3_bram_ramif_wrapper > (vacc_brams_test_vacc_subsys_i_i_3_bram_ramif) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:341 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk_wrapper > (vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:353 - > Running XST synthesis > vacc_brams_test_vacc_subsys_i_i_3_bram_wrapper > (vacc_brams_test_vacc_subsys_i_i_3_bram) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:360 - > Running XST synthesis > > Running NGCBUILD ... > opb_selectmap_fifo_0_wrapper (opb_selectmap_fifo_0) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:27 - > Running NGCBUILD > vacc_brams_test_xsg_core_config_wrapper > (vacc_brams_test_xsg_core_config) - > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base\system.mhs:222 - > Running NGCBUILD > > Rebuilding cache ... > Total run time: 442.00 seconds > Running synthesis.. > bash -c "cd synthesis; ./synthesis.sh; cd .. > Release 7.1.04i - xst H.42 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > --> > TABLE OF CONTENTS > 1) Synthesis Options Summary > 2) HDL Compilation > 3) HDL Analysis > 4) HDL Synthesis > 5) Advanced HDL Synthesis > 5.1) HDL Synthesis Report > 6) Low Level Synthesis > 7) Final Report > 7.1) Device utilization summary > 7.2) TIMING REPORT > > > ========================================================================= > * Synthesis Options Summary * > ========================================================================= > ---- Source Parameters > Input Format : MIXED > Input File Name : "system_xst.prj" > > ---- Target Parameters > Target Device : xc2vp70ff1704-7 > Output File Name : "../implementation/system.ngc" > > ---- Source Options > Top Module Name : system > > ---- Target Options > Add IO Buffers : NO > > ---- General Options > Optimization Goal : speed > RTL Output : YES > Hierarchy Separator : / > > ========================================================================= > > WARNING:Xst:29 - Optimization Effort not specified > The following parameters have been added: > Optimization Effort : 1 > > ========================================================================= > > ========================================================================= > * HDL Compilation * > ========================================================================= > Compiling vhdl file > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > in > Library work. > Entity <system> compiled. > Entity <system> (Architecture <STRUCTURE>) compiled. > > ========================================================================= > * HDL Analysis * > ========================================================================= > Analyzing Entity <system> (Architecture <STRUCTURE>). > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2379: Generating a Black Box for component <IBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2385: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2393: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2401: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2409: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2417: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2425: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2433: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2441: Generating a Black Box for component <IOBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2449: Generating a Black Box for component <IBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2455: Generating a Black Box for component <IBUF>. > WARNING:Xst:766 - > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd" > line > 2461: Generating a Black Box for component <OBUF>. > Entity <system> analyzed. Unit <system> generated. > > > ========================================================================= > * HDL Synthesis * > ========================================================================= > > Synthesizing Unit <system>. > Related source file is > "c:/RLM/vacc_brams_test/XPS_BEE2_usr_base/synthesis/../hdl/system.vhd". > Unit <system> synthesized. > > > ========================================================================= > * Advanced HDL Synthesis * > ========================================================================= > > Advanced RAM inference ... > Advanced multiplier inference ... > Advanced Registered AddSub inference ... > Dynamic shift register inference ... > > ========================================================================= > HDL Synthesis Report > > Found no macro > ========================================================================= > > ========================================================================= > * Low Level Synthesis * > ========================================================================= > Loading device for application Rf_Device from file '2vp70.nph' in > environment > c:/Xilinx. > > Optimizing unit <system> ... > > Mapping all equations... > Building and optimizing final netlist ... > > ========================================================================= > * Final Report * > ========================================================================= > Final Results > RTL Top Level Output File Name : ../implementation/system.ngr > Top Level Output File Name : ../implementation/system.ngc > Output Format : ngc > Optimization Goal : speed > Keep Hierarchy : no > > Design Statistics > # IOs : 16 > > Cell Usage : > # BELS : 2 > # GND : 1 > # VCC : 1 > # IO Buffers : 12 > # IBUF : 3 > # IOBUF : 8 > # OBUF : 1 > # Others : 29 > # dcm_0_wrapper : 1 > # dcm_1_wrapper : 1 > # dcm_2_wrapper : 1 > # dcm_3_wrapper : 1 > # diffclk_buf_0_wrapper : 1 > # diffclk_buf_1_wrapper : 1 > # jtagppc_0_wrapper : 1 > # opb0_wrapper : 1 > # opb_selectmap_fifo_0_wrapper: 1 > # plb2opb_bridge_0_wrapper : 1 > # plb_bram_if_cntlr_1_bram_wrapper: 1 > # plb_bram_if_cntlr_1_wrapper : 1 > # plb_wrapper : 1 > # ppc405_0_wrapper : 1 > # ppc405_1_wrapper : 1 > # reset_block_wrapper : 1 > # > vacc_brams_test_vacc_subsys_i_i_0_bram_ramblk_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_0_bram_ramif_wrapper: 1 > # vacc_brams_test_vacc_subsys_i_i_0_bram_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_1_bram_ramblk_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_1_bram_ramif_wrapper: 1 > # vacc_brams_test_vacc_subsys_i_i_1_bram_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_2_bram_ramblk_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_2_bram_ramif_wrapper: 1 > # vacc_brams_test_vacc_subsys_i_i_2_bram_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_3_bram_ramblk_wrapper: 1 > # > vacc_brams_test_vacc_subsys_i_i_3_bram_ramif_wrapper: 1 > # vacc_brams_test_vacc_subsys_i_i_3_bram_wrapper: 1 > # vacc_brams_test_xsg_core_config_wrapper: 1 > ========================================================================= > > Device utilization summary: > --------------------------- > > Selected Device : 2vp70ff1704-7 > > Number of bonded IOBs: 16 out of 996 1% > > > ========================================================================= > TIMING REPORT > > NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. > FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT > GENERATED AFTER PLACE-and-ROUTE. > > Clock Information: > ------------------ > No clock signals found in this design > > Timing Summary: > --------------- > Speed Grade: -7 > > Minimum period: No path found > Minimum input arrival time before clock: No path found > Maximum output required time after clock: No path found > Maximum combinational path delay: 2.924ns > > Timing Detail: > -------------- > All values displayed in nanoseconds (ns) > > ========================================================================= > Timing constraint: Default path analysis > Total number of paths / destination ports: 2870 / 2862 > ------------------------------------------------------------------------- > Delay: 2.924ns (Levels of Logic = 1) > Source: opb_selectmap_fifo_0:D_O<0> (PAD) > Destination: SELECTMAP_D<0> (PAD) > > Data Path: opb_selectmap_fifo_0:D_O<0> to SELECTMAP_D<0> > Gate Net > Cell:in->out fanout Delay Delay Logical Name (Net Name) > ---------------------------------------- ------------ > opb_selectmap_fifo_0_wrapper:D_O<0> 1 0.000 > 0.332 > opb_selectmap_fifo_0 (SELECTMAP_D_O<0>) > IOBUF:I->IO 2.592 iobuf_1 (SELECTMAP_D<0>) > ---------------------------------------- > Total 2.924ns (2.592ns logic, 0.332ns route) > (88.7% logic, 11.3% route) > > ========================================================================= > CPU : 17.54 / 17.71 s | Elapsed : 17.00 / 17.00 s > > --> > > Total memory usage is 203064 kilobytes > > Number of errors : 0 ( 0 filtered) > Number of warnings : 13 ( 0 filtered) > Number of infos : 0 ( 0 filtered) > > Copying Xilinx Implementation tool scripts. > ******************************************** > Running Xilinx Implementation tools. > ******************************************** > xflow -wd implementation -p xc2vp70ff1704-7 -implement fast_runtime.opt > system.ng > Release 7.1.04i - Xflow H.38 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > xflow.exe -wd implementation -p xc2vp70ff1704-7 -implement fast_runtime.opt > system.ngc > .... Copying flowfile c:/Xilinx/xilinx/data/fpga.flw into working directory > C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation > > Using Flow File: > C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/fpga.flw > Using Option File(s): > > C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/fast_runtime.opt > > Creating Script File ... > > #----------------------------------------------# > # Starting program ngdbuild > # ngdbuild -p xc2vp70ff1704-7 -nt timestamp -bm system.bmm > C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/system.ngc > -uc > system.ucf system.ngd > #----------------------------------------------# > Release 7.1.04i - ngdbuild H.42 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > Command Line: ngdbuild -p xc2vp70ff1704-7 -nt timestamp -bm system.bmm -uc > system.ucf > C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/system.ngc > system.ngd > > Reading NGO file > 'C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/system.ngc' > ... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_1_bram_ramblk_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_1_bram_ramif_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_0_bram_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_0_bram_ramblk_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/plb_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/opb0_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/diffclk_buf_0_wrapper.n > gc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/diffclk_buf_1_wrapper.n > gc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_xsg_cor > e_config_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_0_bram_ramif_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/opb_selectmap_fifo_0_wr > apper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/reset_block_wrapper.ngc > "... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/dcm_0_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/dcm_1_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/dcm_2_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/dcm_3_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/ppc405_0_wrapper.ngc".. > . > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/ppc405_1_wrapper.ngc".. > . > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/jtagppc_0_wrapper.ngc". > .. > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/plb_bram_if_cntlr_1_bra > m_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/plb_bram_if_cntlr_1_wra > pper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/plb2opb_bridge_0_wrappe > r.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_3_bram_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_3_bram_ramblk_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_3_bram_ramif_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_2_bram_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_2_bram_ramblk_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_2_bram_ramif_wrapper.ngc"... > Loading design module > "C:/RLM/vacc_brams_test/XPS_BEE2_usr_base/implementation/vacc_brams_test_vacc_su > bsys_i_i_1_bram_wrapper.ngc"... > > Applying constraints in "system.ucf" to the design... > > Checking timing specifications ... > INFO:XdmHelpers:851 - TNM "usrclk_in", used in period specification > "TS_usrclk_in", was traced into DCM instance "dcm_2/dcm_2/DCM_INST". The > following new TNM groups and period specifications were generated at the > DCM > output(s): > CLK2X: TS_dcm_2_dcm_2_CLK2X_BUF=PERIOD > dcm_2_dcm_2_CLK2X_BUF > TS_usrclk_in*2.000000 HIGH 50.000000% > INFO:XdmHelpers:851 - TNM "dcm_clk_s", used in period specification > "TS_dcm_clk_s", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The > following new TNM groups and period specifications were generated at the > DCM > output(s): > CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF > TS_dcm_clk_s*1.000000 HIGH 50.000000% > CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD > dcm_0_dcm_0_CLK2X_BUF > TS_dcm_clk_s/2.000000 HIGH 50.000000% > CLKFX: TS_dcm_0_dcm_0_CLKFX_BUF=PERIOD > dcm_0_dcm_0_CLKFX_BUF > TS_dcm_clk_s/3.000000 HIGH 50.000000% > INFO:XdmHelpers:851 - TNM "dcm_2_dcm_2_CLK2X_BUF", used in period > specification > "TS_dcm_2_dcm_2_CLK2X_BUF", was traced into DCM instance > "dcm_3/dcm_3/DCM_INST". The following new TNM groups and period > specifications were generated at the DCM output(s): > CLK0: TS_dcm_3_dcm_3_CLK0_BUF=PERIOD dcm_3_dcm_3_CLK0_BUF > TS_dcm_2_dcm_2_CLK2X_BUF*1.000000 HIGH 50.000000% > INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLK2X_BUF", used in period > specification > "TS_dcm_0_dcm_0_CLK2X_BUF", was traced into DCM instance > "dcm_1/dcm_1/DCM_INST". The following new TNM groups and period > specifications were generated at the DCM output(s): > <none> (no matching synchronous elements driven by DCM outputs) > > Processing BMM file ... > > Checking expanded design ... > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_ADDR > ESS_COUNTER/I_SIZE_S_H_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_ADDR > ESS_COUNTER/I_SIZE_S_H_REG1' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_CS_SIZE_REG2' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_CS_SIZE_REG1' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_CS_SIZE_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_BKEND_WRCE_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_BKEND_RDCE_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_BKEND_CE_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_ADDR_S_H_REG1' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_ADDR_S_H_REG0' has unconnected output pin > WARNING:NgdBuild:443 - SFF primitive > > 'plb_bram_if_cntlr_1/plb_bram_if_cntlr_1/I_PLB_IPIF/I_SLAVE_ATTACHMENT/I_DECO > DER/I_ADDR_S_H_REG2' has unconnected output pin > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_assert<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_assert<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_full_thresh_negate<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/WrFifo > /BU2/prog_empty_thresh_negate<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_assert<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_assert<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_full_thresh_negate<0>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<6>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<5>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<4>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<3>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<2>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<1>' has no driver > WARNING:NgdBuild:452 - logical net > > 'opb_selectmap_fifo_0/opb_selectmap_fifo_0/USER_LOGIC_I/selectmap_fifo/RdFifo > /BU2/prog_empty_thresh_negate<0>' has no driver > WARNING:NgdBuild:478 - clock net dcm_0/CLK90 with clock driver > dcm_0/dcm_0/CLK90_BUFG_INST drives no clock pins > WARNING:NgdBuild:478 - clock net dcm_1/CLK90 with clock driver > dcm_1/dcm_1/CLK90_BUFG_INST drives no clock pins > WARNING:NgdBuild:478 - clock net dcm_2/CLK90 with clock driver > dcm_2/dcm_2/CLK90_BUFG_INST drives no clock pins > WARNING:NgdBuild:478 - clock net dcm_3/CLK90 with clock driver > dcm_3/dcm_3/CLK90_BUFG_INST drives no clock pins > > NGDBUILD Design Results Summary: > Number of errors: 0 > Number of warnings: 99 > > Writing NGD file "system.ngd" ... > > Writing NGDBUILD log file "system.bld"... > > NGDBUILD done. > > > > #----------------------------------------------# > # Starting program map > # map -o system_map.ncd -pr b system.ngd system.pcf > #----------------------------------------------# > Release 7.1.04i - Map H.42 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > Using target part "2vp70ff1704-7". > Mapping design into LUTs... > Writing file system_map.ngm... > Running directed packing... > Running delay-based LUT packing... > Running related packing... > Writing design file "system_map.ncd"... > > Design Summary: > Number of errors: 0 > Number of warnings: 10 > Logic Utilization: > Number of Slice Flip Flops: 2,214 out of 66,176 3% > Number of 4 input LUTs: 2,933 out of 66,176 4% > Logic Distribution: > Number of occupied Slices: 2,554 out of 33,088 7% > Number of Slices containing only related logic: 2,554 out of 2,554 > 100% > Number of Slices containing unrelated logic: 0 out of 2,554 > 0% > *See NOTES below for an explanation of the effects of unrelated > logic > Total Number 4 input LUTs: 3,640 out of 66,176 5% > Number used as logic: 2,933 > Number used as a route-thru: 462 > Number used for Dual Port RAMs: 210 > (Two LUTs used per Dual Port RAM) > Number used as Shift registers: 35 > > Number of bonded IOBs: 16 out of 996 1% > IOB Flip Flops: 18 > IOB Master Pads: 2 > IOB Slave Pads: 2 > Number of PPC405s: 2 out of 2 100% > Number of JTAGPPCs: 1 out of 1 100% > Number of Block RAMs: 58 out of 328 17% > Number of GCLKs: 5 out of 16 31% > Number of DCMs: 3 out of 8 37% > Number of GTs: 0 out of 20 0% > Number of GT10s: 0 out of 0 0% > > Number of RPM macros: 9 > Total equivalent gate count for design: 3,893,736 > Additional JTAG gate count for IOBs: 768 > Peak Memory Usage: 263 MB > > NOTES: > > Related logic is defined as being logic that shares connectivity - e.g. > two > LUTs are "related" if they share common inputs. When assembling slices, > Map gives priority to combine logic that is related. Doing so results in > the best timing performance. > > Unrelated logic shares no connectivity. Map will only begin packing > unrelated logic into a slice once 99% of the slices are occupied through > related logic packing. > > Note that once logic distribution reaches the 99% level through related > logic packing, this does not mean the device is completely utilized. > Unrelated logic packing will then begin, continuing until all usable LUTs > and FFs are occupied. Depending on your timing budget, increased levels > of > unrelated logic packing may adversely affect the overall timing > performance > of your design. > > Mapping completed. > See MAP report file "system_map.mrp" for details. > > > > #----------------------------------------------# > # Starting program par > # par -w -ol high system_map.ncd system.ncd system.pcf > #----------------------------------------------# > Release 7.1.04i - par H.42 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > > > Constraints file: system.pcf. > Loading device for application Rf_Device from file '2vp70.nph' in > environment > c:/Xilinx. > "system" is an NCD, version 3.1, device xc2vp70, package ff1704, speed -7 > > Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to > 100.000 > Celsius) > Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 > Volts) > > WARNING:Timing:2666 - Constraint ignored: PATH "TS_RST2_path" TIG; > > Device speed data version: "PRODUCTION 1.91 2005-07-22". > > > Device Utilization Summary: > > Number of BUFGMUXs 5 out of 16 31% > Number of DCMs 3 out of 8 37% > Number of External DIFFMs 2 out of 496 1% > Number of LOCed DIFFMs 2 out of 2 100% > > Number of External DIFFSs 2 out of 496 1% > Number of LOCed DIFFSs 2 out of 2 100% > > Number of External IOBs 12 out of 996 1% > Number of LOCed IOBs 12 out of 12 100% > > Number of JTAGPPCs 1 out of 1 100% > Number of PPC405s 2 out of 2 100% > Number of RAMB16s 58 out of 328 17% > Number of SLICEs 2554 out of 33088 7% > > > Overall effort level (-ol): High (set by user) > Placer effort level (-pl): High (set by user) > Placer cost table entry (-t): 1 > Router effort level (-rl): High (set by user) > > Starting initial Timing Analysis. REAL time: 10 secs > ERROR:Par:228 - At least one timing constraint is impossible to meet > because > component delays alone exceed the constraint. A physical timing > constraint > summary follows. This summary will show a MINIMUM net delay for the > paths. > The "Actual" delays listed in this summary are the UNROUTED delays with a > 100 > ps timing budget for each route, NOT the achieved timing. Any constraint > in > the summary showing a failure ("*" in the first column) has a constraint > that > is too tight. These constraints must be relaxed before PAR can continue. > Please use the Timing Analyzer (GUI) or TRCE (command line) with the > Mapped > NCD and PCF files to identify the problem paths. For more information > about > the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; > for > more information on TRCE, consult the Xilinx Development System Reference > Guide "TRACE" chapter. > > Asterisk (*) preceding a constraint indicates it was not met. > This may be due to a setup or hold violation. > > ------------------------------------------------------------------------------- > - > Constraint | Requested | Actual | > Logic > | | | > Levels > -------------------------------------------------------------------------------- > TS_dcm_clk_s = PERIOD TIMEGRP "dcm_clk_s" | N/A | N/A | N/A > 9.999 ns HIGH 50% | | | > -------------------------------------------------------------------------------- > PATH "TS_RST1_path" TIG | N/A | 1.586ns | 0 > -------------------------------------------------------------------------------- > PATH "TS_RST2_path" TIG | N/A | N/A | N/A > -------------------------------------------------------------------------------- > PATH "TS_RST3_path" TIG | N/A | 0.628ns | 0 > -------------------------------------------------------------------------------- > TS_usrclk_in = PERIOD TIMEGRP "usrclk_in" | N/A | N/A | N/A > 100 MHz HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_2_dcm_2_CLK2X_BUF = PERIOD TIMEGRP | N/A | N/A | N/A > "dcm_2_dcm_2_CLK2X_BUF" TS_usrclk_in | | | > * 2 HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 9.999ns | 5.219ns | 10 > "dcm_0_dcm_0_CLK0_BUF" TS_dcm_clk_s | | | > HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP | N/A | N/A | N/A > "dcm_0_dcm_0_CLKFX_BUF" TS_dcm_clk_s | | | > / 3 HIGH 50% | | | > -------------------------------------------------------------------------------- > * TS_dcm_3_dcm_3_CLK0_BUF = PERIOD TIMEGRP | 5.000ns | 10.093ns | 35 > "dcm_3_dcm_3_CLK0_BUF" TS_dcm_2_d | | | > cm_2_CLK2X_BUF HIGH 50% | | | > -------------------------------------------------------------------------------- > > > 1 constraint not met. > INFO:Timing:2761 - N/A entries in the Constraints list may indicate that > the > constraint does not cover any paths or that it has no requested value. > > Generating "PAR" statistics. > > ************************** > Generating Clock Report > ************************** > > +---------------------+--------------+------+------+------------+-------------+ > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > Delay(ns)| > +---------------------+--------------+------+------+------------+-------------+ > | usr_clk2x* | Global| No | 486 | 0.000 | > | > +---------------------+--------------+------+------+------------+-------------+ > | plb_bram_BRAM_Clk* | Global| No | 1010 | 0.000 | > | > +---------------------+--------------+------+------+------------+-------------+ > | sys_clk3x* | Global| No | 1 | 0.000 | > | > +---------------------+--------------+------+------+------------+-------------+ > |jtagppc_0_0_JTGC405T | | | | | > | > | CK* | Global| No | 2 | 0.000 | > | > +---------------------+--------------+------+------+------------+-------------+ > * Some of the Clock networks are NOT completely routed > > Timing Score: 773533 > > INFO:Par:62 - Your design did not meet timing. The following are some > suggestions to assist you to meet timing in your design. > > > Review the timing report using Timing Analyzer (In ISE select "Post-Place > & Route Static Timing Report"). Go to the failing constraint(s) and > select > the "Timing Improvement Wizard" link for suggestions to correct each > problem. > > Rerun Map with "-timing" (ISE process "Perform Timing -Driven Packing and > Placement" > > Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" > (ISE process "Multi Pass Place & Route"). > > Visit the Xilinx technical support web at http://support.xilinx.com and > go > to either "Troubleshoot->Tech Tips->Timing & Constraints" or > " TechXclusives->Timing Closure" for tips and suggestions for meeting > timing > in your design. > > Asterisk (*) preceding a constraint indicates it was not met. > This may be due to a setup or hold violation. > > ------------------------------------------------------------------------------- > - > Constraint | Requested | Actual | > Logic > | | | > Levels > -------------------------------------------------------------------------------- > TS_dcm_clk_s = PERIOD TIMEGRP "dcm_clk_s" | N/A | N/A | N/A > 9.999 ns HIGH 50% | | | > -------------------------------------------------------------------------------- > PATH "TS_RST1_path" TIG | N/A | 1.586ns | 0 > -------------------------------------------------------------------------------- > PATH "TS_RST2_path" TIG | N/A | N/A | N/A > -------------------------------------------------------------------------------- > PATH "TS_RST3_path" TIG | N/A | 0.628ns | 0 > -------------------------------------------------------------------------------- > TS_usrclk_in = PERIOD TIMEGRP "usrclk_in" | N/A | N/A | N/A > 100 MHz HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_2_dcm_2_CLK2X_BUF = PERIOD TIMEGRP | N/A | N/A | N/A > "dcm_2_dcm_2_CLK2X_BUF" TS_usrclk_in | | | > * 2 HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 9.999ns | 5.219ns | 10 > "dcm_0_dcm_0_CLK0_BUF" TS_dcm_clk_s | | | > HIGH 50% | | | > -------------------------------------------------------------------------------- > TS_dcm_0_dcm_0_CLKFX_BUF = PERIOD TIMEGRP | N/A | N/A | N/A > "dcm_0_dcm_0_CLKFX_BUF" TS_dcm_clk_s | | | > / 3 HIGH 50% | | | > -------------------------------------------------------------------------------- > * TS_dcm_3_dcm_3_CLK0_BUF = PERIOD TIMEGRP | 5.000ns | 10.093ns | 35 > "dcm_3_dcm_3_CLK0_BUF" TS_dcm_2_d | | | > cm_2_CLK2X_BUF HIGH 50% | | | > -------------------------------------------------------------------------------- > > > 1 constraint not met. > INFO:Timing:2761 - N/A entries in the Constraints list may indicate that > the > constraint does not cover any paths or that it has no requested value. > Generating Pad Report. > > 6476 signals are not completely routed. > > WARNING:Par:100 - Design is not completely routed. > > Total REAL time to PAR completion: 19 secs > Total CPU time to PAR completion: 16 secs > > Peak Memory Usage: 233 MB > > Placement: Completed - errors found. > Routing: Completed - errors found. > Timing: Completed - 240 errors found. > > Number of error messages: 1 > Number of warning messages: 2 > Number of info messages: 1 > > Writing design to file system.ncd > > > > PAR done! > ERROR:Xflow - Program par returned error code 31. Aborting flow > execution... > make: *** [implementation/system.bit] Error > ERROR:MDT - Error while running "make -f system.make init_bram" > No changes to be saved in MSS file > Saved project XMP file > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bit > ..\bit_files\vacc_brams_test_2008_Apr_11_1007.bit > The system cannot find the file specified. > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>mkbof.exe -o > implementation\download.bof -s core_info.tab -v implementation\download.bit > elf=(null), bit=implementation\download.bit, > sym=core_info.tab, bof=implementation\download.bof > elf size = 4096 > bit file open failed > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bof > ..\bit_files\vacc_brams_test_floating_2008_Apr_11_1007.bof > The system cannot find the file specified. > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>mkbof.exe -o > implementation\download.bof -s core_info.tab -p 0 -v > implementation\download.bit > elf=(null), bit=implementation\download.bit, > sym=core_info.tab, bof=implementation\download.bof > elf size = 4096 > bit file open failed > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bof > ..\bit_files\vacc_brams_test_fpga1_2008_Apr_11_1007.bof > The system cannot find the file specified. > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>mkbof.exe -o > implementation\download.bof -s core_info.tab -p 1 -v > implementation\download.bit > elf=(null), bit=implementation\download.bit, > sym=core_info.tab, bof=implementation\download.bof > elf size = 4096 > bit file open failed > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bof > ..\bit_files\vacc_brams_test_fpga2_2008_Apr_11_1007.bof > The system cannot find the file specified. > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>mkbof.exe -o > implementation\download.bof -s core_info.tab -p 2 -v > implementation\download.bit > elf=(null), bit=implementation\download.bit, > sym=core_info.tab, bof=implementation\download.bof > elf size = 4096 > bit file open failed > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bof > ..\bit_files\vacc_brams_test_fpga3_2008_Apr_11_1007.bof > The system cannot find the file specified. > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>mkbof.exe -o > implementation\download.bof -s core_info.tab -p 3 -v > implementation\download.bit > elf=(null), bit=implementation\download.bit, > sym=core_info.tab, bof=implementation\download.bof > elf size = 4096 > bit file open failed > > C:\RLM\vacc_brams_test\XPS_BEE2_usr_base>copy > implementation\download.bof > ..\bit_files\vacc_brams_test_fpga4_2008_Apr_11_1007.bof > The system cannot find the file specified. > Error using ==> gen_xps_files > Programation files generation failed, EDK compilation probably also failed. > >> > Model { > Name "vacc_brams_test" > Version 6.2 > MdlSubVersion 0 > GraphicalInterface { > NumRootInports 0 > NumRootOutports 0 > ParameterArgumentNames "" > ComputedModelVersion "1.20" > NumModelReferences 0 > NumTestPointedSignals 0 > } > SavedCharacterEncoding "ibm-5348_P100-1997" > SaveDefaultBlockParams on > SampleTimeColors off > LibraryLinkDisplay "none" > WideLines off > ShowLineDimensions off > ShowPortDataTypes on > ShowLoopsOnError on > IgnoreBidirectionalLines off > ShowStorageClass off > ShowTestPointIcons on > ShowViewerIcons on > SortedOrder off > ExecutionContextIcon off > ShowLinearizationAnnotations on > RecordCoverage off > CovPath "/" > CovSaveName "covdata" > CovMetricSettings "dw" > CovNameIncrementing off > CovHtmlReporting on > covSaveCumulativeToWorkspaceVar on > CovSaveSingleToWorkspaceVar on > CovCumulativeVarName "covCumulativeData" > CovCumulativeReport off > CovReportOnPause on > ScopeRefreshTime 0.035000 > OverrideScopeRefreshTime on > DisableAllScopes off > DataTypeOverride "UseLocalSettings" > MinMaxOverflowLogging "UseLocalSettings" > MinMaxOverflowArchiveMode "Overwrite" > BlockNameDataTip off > BlockParametersDataTip off > BlockDescriptionStringDataTip off > ToolBar on > StatusBar on > BrowserShowLibraryLinks off > BrowserLookUnderMasks off > Created "Thu Apr 10 14:35:25 2008" > UpdateHistory "UpdateHistoryNever" > ModifiedByFormat "%<Auto>" > LastModifiedBy "rmccullo" > ModifiedDateFormat "%<Auto>" > LastModifiedDate "Fri Apr 11 10:35:05 2008" > ModelVersionFormat "1.%<AutoIncrement:20>" > ConfigurationManager "None" > LinearizationMsg "none" > Profile off > ParamWorkspaceSource "MATLABWorkspace" > AccelSystemTargetFile "accel.tlc" > AccelTemplateMakefile "accel_default_tmf" > AccelMakeCommand "make_rtw" > TryForcingSFcnDF off > ExtModeBatchMode off > ExtModeEnableFloating on > ExtModeTrigType "manual" > ExtModeTrigMode "normal" > ExtModeTrigPort "1" > ExtModeTrigElement "any" > ExtModeTrigDuration 1000 > ExtModeTrigDurationFloating "auto" > ExtModeTrigHoldOff 0 > ExtModeTrigDelay 0 > ExtModeTrigDirection "rising" > ExtModeTrigLevel 0 > ExtModeArchiveMode "off" > ExtModeAutoIncOneShot off > ExtModeIncDirWhenArm off > ExtModeAddSuffixToVar off > ExtModeWriteAllDataToWs off > ExtModeArmWhenConnect on > ExtModeSkipDownloadWhenConnect off > ExtModeLogAll on > ExtModeAutoUpdateStatusClock on > BufferReuse on > StrictBusMsg "None" > ProdHWDeviceType "32-bit Generic" > ShowModelReferenceBlockVersion off > ShowModelReferenceBlockIO off > Array { > Type "Handle" > Dimension 1 > Simulink.ConfigSet { > $ObjectID 1 > Version "1.1.0" > Array { > Type "Handle" > Dimension 7 > Simulink.SolverCC { > $ObjectID 2 > Version "1.1.0" > StartTime "0.0" > StopTime "20000" > AbsTol "auto" > FixedStep "auto" > InitialStep "auto" > MaxNumMinSteps "-1" > MaxOrder 5 > ExtrapolationOrder 4 > NumberNewtonIterations 1 > MaxStep "auto" > MinStep "auto" > RelTol "1e-3" > SolverMode "Auto" > Solver "ode45" > SolverName "ode45" > ZeroCrossControl "UseLocalSettings" > AlgebraicLoopSolver "TrustRegion" > SolverResetMethod "Fast" > PositivePriorityOrder off > AutoInsertRateTranBlk off > SampleTimeConstraint "Unconstrained" > RateTranMode "Deterministic" > } > Simulink.DataIOCC { > $ObjectID 3 > Version "1.1.0" > Decimation "1" > ExternalInput "[t, u]" > FinalStateName "xFinal" > InitialState "xInitial" > LimitDataPoints on > MaxDataPoints "1000" > LoadExternalInput off > LoadInitialState off > SaveFinalState off > SaveFormat "Array" > SaveOutput on > SaveState off > SignalLogging on > SaveTime on > StateSaveName "xout" > TimeSaveName "tout" > OutputSaveName "yout" > SignalLoggingName "logsout" > OutputOption "RefineOutputTimes" > OutputTimes "[]" > Refine "1" > } > Simulink.OptimizationCC { > $ObjectID 4 > Array { > Type "Cell" > Dimension 5 > Cell "ZeroExternalMemoryAtStartup" > Cell "ZeroInternalMemoryAtStartup" > Cell "InitFltsAndDblsToZero" > Cell "OptimizeModelRefInitCode" > Cell "NoFixptDivByZeroProtection" > PropName "DisabledProps" > } > Version "1.1.0" > BlockReduction on > BooleanDataType on > ConditionallyExecuteInputs on > InlineParams off > InlineInvariantSignals off > OptimizeBlockIOStorage on > BufferReuse on > EnforceIntegerDowncast on > ExpressionFolding on > FoldNonRolledExpr on > LocalBlockOutputs on > ParameterPooling on > RollThreshold 5 > SystemCodeInlineAuto off > StateBitsets off > DataBitsets off > UseTempVars off > ZeroExternalMemoryAtStartup on > ZeroInternalMemoryAtStartup on > InitFltsAndDblsToZero on > NoFixptDivByZeroProtection off > EfficientFloat2IntCast off > OptimizeModelRefInitCode off > LifeSpan "inf" > BufferReusableBoundary on > } > Simulink.DebuggingCC { > $ObjectID 5 > Version "1.1.0" > RTPrefix "error" > ConsistencyChecking "none" > ArrayBoundsChecking "none" > SignalInfNanChecking "none" > AlgebraicLoopMsg "warning" > ArtificialAlgebraicLoopMsg "warning" > CheckSSInitialOutputMsg on > CheckExecutionContextPreStartOutputMsg off > CheckExecutionContextRuntimeOutputMsg off > SignalResolutionControl "TryResolveAllWithWarning" > BlockPriorityViolationMsg "warning" > MinStepSizeMsg "warning" > SolverPrmCheckMsg "warning" > InheritedTsInSrcMsg "warning" > DiscreteInheritContinuousMsg "warning" > MultiTaskDSMMsg "warning" > MultiTaskRateTransMsg "error" > SingleTaskRateTransMsg "none" > TasksWithSamePriorityMsg "warning" > CheckMatrixSingularityMsg "none" > IntegerOverflowMsg "warning" > Int32ToFloatConvMsg "warning" > ParameterDowncastMsg "error" > ParameterOverflowMsg "error" > ParameterPrecisionLossMsg "warning" > UnderSpecifiedDataTypeMsg "none" > UnnecessaryDatatypeConvMsg "none" > VectorMatrixConversionMsg "none" > InvalidFcnCallConnMsg "error" > FcnCallInpInsideContextMsg "Use local settings" > SignalLabelMismatchMsg "none" > UnconnectedInputMsg "warning" > UnconnectedOutputMsg "warning" > UnconnectedLineMsg "warning" > SFcnCompatibilityMsg "none" > UniqueDataStoreMsg "none" > BusObjectLabelMismatch "warning" > RootOutportRequireBusObject "warning" > AssertControl "UseLocalSettings" > EnableOverflowDetection off > ModelReferenceIOMsg "none" > ModelReferenceVersionMismatchMessage "none" > ModelReferenceIOMismatchMessage "none" > ModelReferenceCSMismatchMessage "none" > ModelReferenceSimTargetVerbose off > UnknownTsInhSupMsg "warning" > ModelReferenceDataLoggingMessage "warning" > ModelReferenceSymbolNameMessage "warning" > ModelReferenceExtraNoncontSigs "error" > } > Simulink.HardwareCC { > $ObjectID 6 > Version "1.1.0" > ProdBitPerChar 8 > ProdBitPerShort 16 > ProdBitPerInt 32 > ProdBitPerLong 32 > ProdIntDivRoundTo "Undefined" > ProdEndianess "Unspecified" > ProdWordSize 32 > ProdShiftRightIntArith on > ProdHWDeviceType "32-bit Generic" > TargetBitPerChar 8 > TargetBitPerShort 16 > TargetBitPerInt 32 > TargetBitPerLong 32 > TargetShiftRightIntArith on > TargetIntDivRoundTo "Undefined" > TargetEndianess "Unspecified" > TargetWordSize 32 > TargetTypeEmulationWarnSuppressLevel 0 > TargetPreprocMaxBitsSint 32 > TargetPreprocMaxBitsUint 32 > TargetHWDeviceType "Specified" > TargetUnknown off > ProdEqTarget on > } > Simulink.ModelReferenceCC { > $ObjectID 7 > Version "1.1.0" > UpdateModelReferenceTargets > "IfOutOfDateOrStructuralChange" > CheckModelReferenceTargetMessage "error" > ModelReferenceNumInstancesAllowed "Multi" > ModelReferencePassRootInputsByReference on > ModelReferenceMinAlgLoopOccurrences off > } > Simulink.RTWCC { > $BackupClass "Simulink.RTWCC" > $ObjectID 8 > Array { > Type "Cell" > Dimension 1 > Cell "IncludeHyperlinkInReport" > PropName "DisabledProps" > } > Version "1.1.0" > SystemTargetFile "grt.tlc" > GenCodeOnly off > MakeCommand "make_rtw" > TemplateMakefile "grt_default_tmf" > GenerateReport off > SaveLog off > RTWVerbose on > RetainRTWFile off > ProfileTLC off > TLCDebug off > TLCCoverage off > TLCAssert off > ProcessScriptMode "Default" > ConfigurationMode "Optimized" > ConfigAtBuild off > IncludeHyperlinkInReport off > LaunchReport off > TargetLang "C" > Array { > Type "Handle" > Dimension 2 > Simulink.CodeAppCC { > $ObjectID 9 > Array { > Type "Cell" > Dimension 9 > Cell "IgnoreCustomStorageClasses" > Cell "InsertBlockDesc" > Cell "SFDataObjDesc" > Cell "SimulinkDataObjDesc" > Cell "DefineNamingRule" > Cell "SignalNamingRule" > Cell "ParamNamingRule" > Cell "InlinedPrmAccess" > Cell "CustomSymbolStr" > PropName "DisabledProps" > } > Version "1.1.0" > ForceParamTrailComments off > GenerateComments on > IgnoreCustomStorageClasses on > IncHierarchyInIds off > MaxIdLength 31 > PreserveName off > PreserveNameWithParent off > ShowEliminatedStatement off > IncAutoGenComments off > SimulinkDataObjDesc off > SFDataObjDesc off > IncDataTypeInIds off > PrefixModelToSubsysFcnNames on > CustomSymbolStr "$R$N$M" > MangleLength 1 > DefineNamingRule "None" > ParamNamingRule "None" > SignalNamingRule "None" > InsertBlockDesc off > SimulinkBlockComments on > EnableCustomComments off > InlinedPrmAccess "Literals" > ReqsInCode off > } > Simulink.GRTTargetCC { > $BackupClass "Simulink.TargetCC" > $ObjectID 10 > Array { > Type "Cell" > Dimension 12 > Cell "IncludeMdlTerminateFcn" > Cell "CombineOutputUpdateFcns" > Cell "SuppressErrorStatus" > Cell "ERTCustomFileBanners" > Cell "GenerateSampleERTMain" > Cell "MultiInstanceERTCode" > Cell "PurelyIntegerCode" > Cell "SupportNonFinite" > Cell "SupportComplex" > Cell "SupportAbsoluteTime" > Cell "SupportContinuousTime" > Cell "SupportNonInlinedSFcns" > PropName "DisabledProps" > } > Version "1.1.0" > TargetFcnLib "ansi_tfl_tmw.mat" > TargetLibSuffix "" > TargetPreCompLibLocation "" > GenFloatMathFcnCalls "ANSI_C" > UtilityFuncGeneration "Auto" > GenerateFullHeader on > GenerateSampleERTMain off > IsPILTarget off > ModelReferenceCompliant on > IncludeMdlTerminateFcn on > CombineOutputUpdateFcns off > SuppressErrorStatus off > IncludeFileDelimiter "Auto" > ERTCustomFileBanners off > SupportAbsoluteTime on > LogVarNameModifier "rt_" > MatFileLogging on > MultiInstanceERTCode off > SupportNonFinite on > SupportComplex on > PurelyIntegerCode off > SupportContinuousTime on > SupportNonInlinedSFcns on > ExtMode off > ExtModeStaticAlloc off > ExtModeTesting off > ExtModeStaticAllocSize 1000000 > ExtModeTransport 0 > ExtModeMexFile "ext_comm" > RTWCAPISignals off > RTWCAPIParams off > RTWCAPIStates off > GenerateASAP2 off > } > PropName "Components" > } > } > PropName "Components" > } > Name "Configuration" > SimulationMode "normal" > CurrentDlgPage "Solver" > } > PropName "ConfigurationSets" > } > Simulink.ConfigSet { > $PropName "ActiveConfigurationSet" > $ObjectID 1 > } > BlockDefaults { > Orientation "right" > ForegroundColor "black" > BackgroundColor "white" > DropShadow off > NamePlacement "normal" > FontName "Helvetica" > FontSize 10 > FontWeight "normal" > FontAngle "normal" > ShowName on > } > BlockParameterDefaults { > Block { > BlockType DiscretePulseGenerator > PulseType "Sample based" > TimeSource "Use simulation time" > Amplitude "1" > Period "2" > PulseWidth "1" > PhaseDelay "0" > SampleTime "1" > VectorParams1D on > } > Block { > BlockType Display > Format "short" > Decimation "10" > Floating off > SampleTime "-1" > } > Block { > BlockType From > IconDisplay "Tag" > } > Block { > BlockType Goto > IconDisplay "Tag" > } > Block { > BlockType Inport > UseBusObject off > BusObject "BusObject" > BusOutputAsStruct off > PortDimensions "-1" > SampleTime "-1" > DataType "auto" > OutDataType "sfix(16)" > OutScaling "2^0" > SignalType "auto" > SamplingMode "auto" > Interpolate on > } > Block { > BlockType Outport > Port "1" > UseBusObject off > BusObject "BusObject" > BusOutputAsStruct off > PortDimensions "-1" > SampleTime "-1" > DataType "auto" > OutDataType "sfix(16)" > OutScaling "2^0" > SignalType "auto" > SamplingMode "auto" > OutputWhenDisabled "held" > InitialOutput "[]" > } > Block { > BlockType Reference > } > Block { > BlockType Scope > Floating off > ModelBased off > TickLabels "OneTimeTick" > ZoomMode "on" > Grid "on" > TimeRange "auto" > YMin "-5" > YMax "5" > SaveToWorkspace off > SaveName "ScopeData" > LimitDataPoints on > MaxDataPoints "5000" > Decimation "1" > SampleInput off > SampleTime "0" > } > Block { > BlockType "S-Function" > FunctionName "system" > SFunctionModules "''" > PortCounts "[]" > } > Block { > BlockType SubSystem > ShowPortLabels on > Permissions "ReadWrite" > PermitHierarchicalResolution "All" > SystemSampleTime "-1" > RTWFcnNameOpts "Auto" > RTWFileNameOpts "Auto" > SimViewingDevice off > DataTypeOverride "UseLocalSettings" > MinMaxOverflowLogging "UseLocalSettings" > } > Block { > BlockType Terminator > } > } > AnnotationDefaults { > HorizontalAlignment "center" > VerticalAlignment "middle" > ForegroundColor "black" > BackgroundColor "white" > DropShadow off > FontName "Helvetica" > FontSize 10 > FontWeight "normal" > FontAngle "normal" > } > LineDefaults { > FontName "Helvetica" > FontSize 9 > FontWeight "normal" > FontAngle "normal" > } > System { > Name "vacc_brams_test" > Location [85, 114, 1298, 999] > Open on > ModelBrowserVisibility off > ModelBrowserWidth 200 > ScreenColor "white" > PaperOrientation "landscape" > PaperPositionMode "auto" > PaperType "usletter" > PaperUnits "inches" > ZoomFactor "82" > ReportName "simulink-default.rpt" > Block { > BlockType Reference > Name " System Generator" > Tag "genX" > Ports [] > Position [27, 28, 78, 78] > ShowName off > AttributesFormatString "System\\nGenerator" > UserDataPersistent on > UserData "DataTag0" > SourceBlock "xbsIndex_r3/ System Generator" > SourceType "Xilinx System Generator" > ShowPortLabels on > xilinxfamily "Virtex2P" > part "xc2vp70" > speed "-7" > package "ff1704" > synthesis_tool "XST" > directory "./vacc_brams_test/sysgen" > testbench off > simulink_period "1" > sysclk_period "5" > incr_netlist off > trim_vbits "Everywhere in SubSystem" > dbl_ovrd "According to Block Masks" > core_generation "According to Block Masks" > run_coregen off > deprecated_control off > eval_field "0" > } > Block { > BlockType Reference > Name "1PPS_sync_counter" > Ports [0, 1] > Position [100, 185, 150, 235] > NamePlacement "alternate" > SourceBlock "xbsIndex_r3/Counter" > SourceType "Xilinx Counter Block" > cnt_type "Free Running" > n_bits "32" > bin_pt "0" > arith_type "Unsigned" > start_count "0" > cnt_to "Inf" > cnt_by_val "1" > operation "Up" > explicit_period off > period "1" > load_pin off > rst off > en off > dbl_ovrd off > show_param off > use_rpm on > gen_core off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out1" > Ports [1, 1] > Position [985, 199, 1040, 221] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out10" > Ports [1, 1] > Position [985, 94, 1040, 116] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out11" > Ports [1, 1] > Position [985, 59, 1040, 81] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out12" > Ports [1, 1] > Position [985, 164, 1040, 186] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out13" > Ports [1, 1] > Position [985, 129, 1040, 151] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Gateway Out2" > Ports [1, 1] > Position [985, 234, 1040, 256] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port on > timing_constraint "None" > locs_specified off > LOCs "{}" > needs_fixed_name off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Terminator > Name "I_0_out_terminator" > Position [695, 360, 715, 380] > } > Block { > BlockType Terminator > Name "I_1_out_terminator" > Position [695, 470, 715, 490] > } > Block { > BlockType Terminator > Name "I_2_out_terminator" > Position [695, 580, 715, 600] > } > Block { > BlockType Terminator > Name "I_3_out_terminator" > Position [695, 690, 715, 710] > } > Block { > BlockType Reference > Name "Logical" > Ports [2, 1] > Position [665, 858, 715, 922] > SourceBlock "xbsIndex_r3/Logical" > SourceType "Xilinx Logical Block" > logical_function "OR" > inputs "2" > precision "Full" > arith_type "Unsigned" > n_bits "8" > bin_pt "2" > align_bp on > latency "0" > explicit_period off > period "1" > en off > dbl_ovrd off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "Relational" > Ports [2, 1] > Position [775, 947, 820, 1043] > Orientation "left" > SourceBlock "xbsIndex_r3/Relational" > SourceType "Xilinx Relational Block" > mode "a<b" > latency "0" > explicit_period on > period "-1" > en off > dbl_ovrd off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "XSG core config" > Tag "xps:xsg" > Ports [] > Position [105, 29, 151, 72] > BackgroundColor "[1.000000, 1.000000, 0.000000]" > SourceBlock "xps_library/XSG core config" > SourceType "xsg core config" > ShowPortLabels on > hw_sys "BEE2_usr" > ibob_linux off > clk_src "usr_clk2x" > gpio_clk_io_group "iBOB:sma" > gpio_clk_bit_index "0" > clk_rate "200" > sample_period "1" > synthesis_tool "XST" > mpc_type "powerpc405" > } > Block { > BlockType Reference > Name "acc_length_less_1" > Ports [0, 1] > Position [215, 625, 265, 655] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "15" > equ "P=C" > arith_type "Unsigned" > n_bits "32" > bin_pt "0" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Terminator > Name "brams_full_terminator" > Position [695, 250, 715, 270] > } > Block { > BlockType Reference > Name "end_of_bram" > Ports [0, 1] > Position [885, 1005, 935, 1035] > Orientation "left" > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "511" > equ "P=C" > arith_type "Unsigned" > n_bits "12" > bin_pt "0" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Reference > Name "external_bram_addr_counter" > Ports [2, 1] > Position [775, 808, 825, 917] > SourceBlock "xbsIndex_r3/Counter" > SourceType "Xilinx Counter Block" > cnt_type "Free Running" > n_bits "12" > bin_pt "0" > arith_type "Unsigned" > start_count "0" > cnt_to "Inf" > cnt_by_val "1" > operation "Up" > explicit_period off > period "1" > load_pin off > rst on > en on > dbl_ovrd off > show_param off > use_rpm on > gen_core off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "fake_I_0" > Ports [0, 1] > Position [215, 305, 265, 335] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "10" > equ "P=C" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Reference > Name "fake_I_1" > Ports [0, 1] > Position [215, 385, 265, 415] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "20" > equ "P=C" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Reference > Name "fake_I_2" > Ports [0, 1] > Position [215, 465, 265, 495] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "30" > equ "P=C" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Reference > Name "fake_I_3" > Ports [0, 1] > Position [215, 545, 265, 575] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "40" > equ "P=C" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Reference > Name "generate_1PPS_sync" > Ports [2, 1] > Position [215, 180, 265, 295] > NamePlacement "alternate" > SourceBlock "xbsIndex_r3/Relational" > SourceType "Xilinx Relational Block" > mode "a=b" > latency "0" > explicit_period off > period "1" > en off > dbl_ovrd off > show_param off > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area off > } > Block { > BlockType Reference > Name "locus_of_1PPS_sync" > Ports [0, 1] > Position [100, 250, 150, 280] > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "10" > equ "P=C" > arith_type "Unsigned" > n_bits "32" > bin_pt "0" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period on > period "1" > dbl_ovrd off > } > Block { > BlockType Scope > Name "outputs_scope" > Ports [6] > Position [1105, 49, 1160, 266] > Location [83, 293, 1074, 991] > Open off > NumInputPorts "6" > ZoomMode "xonly" > List { > ListType AxesTitles > axes1 "%<SignalLabel>" > axes2 "%<SignalLabel>" > axes3 "%<SignalLabel>" > axes4 "%<SignalLabel>" > axes5 "%<SignalLabel>" > axes6 "%<SignalLabel>" > } > TimeRange "12000" > YMin "-2~-10~-10~-10~-10~-5" > YMax "2~50~50~50~50~5" > SaveName "ScopeData2" > DataFormat "StructureWithTime" > LimitDataPoints off > } > Block { > BlockType SubSystem > Name "vacc_subsys_I" > Ports [7, 5] > Position [330, 202, 510, 758] > TreatAsAtomicUnit off > MinAlgLoopOccurrences off > RTWSystemCode "Auto" > System { > Name "vacc_subsys_I" > Location [-37, 80, 1231, 993] > Open off > ModelBrowserVisibility off > ModelBrowserWidth 200 > ScreenColor "white" > PaperOrientation "landscape" > PaperPositionMode "auto" > PaperType "usletter" > PaperUnits "inches" > ZoomFactor "66" > Block { > BlockType Inport > Name "SYNC" > Position [15, 333, 45, 347] > Port "1" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "I_0_In" > Position [15, 393, 45, 407] > Port "2" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "I_1_In" > Position [15, 428, 45, 442] > Port "3" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "I_2_In" > Position [15, 463, 45, 477] > Port "4" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "I_3_In" > Position [15, 498, 45, 512] > Port "5" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "Acc_len" > Position [15, 563, 45, 577] > Port "6" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "BRAM_ADDR" > Position [15, 933, 45, 947] > Port "7" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Reference > Name "9-bit Addr Cntr1" > Ports [2, 1] > Position [780, 1007, 830, 1123] > Orientation "left" > SourceBlock "xbsIndex_r3/Counter" > SourceType "Xilinx Counter Block" > cnt_type "Free Running" > n_bits "12" > bin_pt "0" > arith_type "Unsigned" > start_count "0" > cnt_to "511" > cnt_by_val "1" > operation "Up" > explicit_period "off" > period "1" > load_pin "off" > rst "on" > en "on" > dbl_ovrd "off" > show_param "off" > use_rpm "on" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Addr MUX" > Ports [3, 1] > Position [790, 907, 815, 973] > SourceBlock "xbsIndex_r3/Mux" > SourceType "Xilinx Multiplexer Block" > inputs "2" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > mux_type "off" > use_rpm "off" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Convert4" > Ports [1, 1] > Position [1325, 420, 1370, 450] > ShowName off > SourceBlock "xbsIndex_r3/Convert" > SourceType "Xilinx Converter Block" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > quantization "Round (unbiased: +/- Inf)" > overflow "Saturate" > latency "0" > explicit_period "off" > period "1" > dbl_ovrd "off" > show_param "off" > inserted_by_tool "off" > pipeline "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Convert5" > Ports [1, 1] > Position [1325, 520, 1370, 550] > ShowName off > SourceBlock "xbsIndex_r3/Convert" > SourceType "Xilinx Converter Block" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > quantization "Round (unbiased: +/- Inf)" > overflow "Saturate" > latency "0" > explicit_period "off" > period "1" > dbl_ovrd "off" > show_param "off" > inserted_by_tool "off" > pipeline "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Convert6" > Ports [1, 1] > Position [1325, 620, 1370, 650] > ShowName off > SourceBlock "xbsIndex_r3/Convert" > SourceType "Xilinx Converter Block" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > quantization "Round (unbiased: +/- Inf)" > overflow "Saturate" > latency "0" > explicit_period "off" > period "1" > dbl_ovrd "off" > show_param "off" > inserted_by_tool "off" > pipeline "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Convert7" > Ports [1, 1] > Position [1325, 720, 1370, 750] > ShowName off > SourceBlock "xbsIndex_r3/Convert" > SourceType "Xilinx Converter Block" > arith_type "Signed (2's comp)" > n_bits "32" > bin_pt "16" > quantization "Round (unbiased: +/- Inf)" > overflow "Saturate" > latency "0" > explicit_period "off" > period "1" > dbl_ovrd "off" > show_param "off" > inserted_by_tool "off" > pipeline "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Delay" > Ports [1, 1] > Position [900, 1141, 940, 1169] > ShowName off > SourceBlock "xbsIndex_r3/Delay" > SourceType "Xilinx Delay Block" > latency "4" > reg_retiming "off" > explicit_period "off" > period "1" > en "off" > accept_only_valid "off" > init_zero "on" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType SubSystem > Name "DisIntegrator1" > Ports [5, 4] > Position [1065, 381, 1175, 789] > TreatAsAtomicUnit off > MinAlgLoopOccurrences off > RTWSystemCode "Auto" > System { > Name "DisIntegrator1" > Location [0, 82, 1251, 983] > Open off > ModelBrowserVisibility off > ModelBrowserWidth 200 > ScreenColor "white" > PaperOrientation "landscape" > PaperPositionMode "auto" > PaperType "usletter" > PaperUnits "inches" > ZoomFactor "100" > Block { > BlockType Inport > Name "In1" > Position [25, 653, 55, 667] > Port "1" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "In2" > Position [25, 1083, 55, 1097] > Port "2" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "In3" > Position [25, 1518, 55, 1532] > Port "3" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "In4" > Position [25, 1953, 55, 1967] > Port "4" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Inport > Name "acc_len_val" > Position [25, 103, 55, 117] > Port "5" > IconDisplay "Port number" > LatchInput off > } > Block { > BlockType Reference > Name "AddSub6" > Ports [2, 1] > Position [385, 43, 435, 132] > SourceBlock "xbsIndex_r3/AddSub" > SourceType "Xilinx Adder/Subtractor" > mode "Addition" > precision "Full" > arith_type "Unsigned" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > use_carryin "off" > use_carryout "off" > en "off" > dbl_ovrd "off" > show_param "off" > use_core "on" > pipeline "off" > use_rpm "on" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Concat" > Ports [3, 1] > Position [1575, 248, 1625, 432] > SourceBlock "xbsIndex_r3/Concat" > SourceType "Xilinx Bus Concatenator" > num_inputs "3" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Constant1" > Ports [0, 1] > Position [265, 50, 310, 80] > ShowName off > SourceBlock "xbsIndex_r3/Constant" > SourceType "Xilinx Constant Block" > const "1" > equ "P=C" > arith_type "Unsigned" > n_bits "32" > bin_pt "0" > opselect "C" > inp2 "PCIN>>17" > opr "+" > inp1 "P" > carry "CIN" > iostate "0" > explicit_period "on" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Display > Name "Display" > Ports [1] > Position [2105, 250, 2195, 280] > Decimation "1" > } > Block { > BlockType Reference > Name "Gateway Out" > Ports [1, 1] > Position [1960, 194, 2015, 216] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out1" > Ports [1, 1] > Position [2620, 119, 2675, 141] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out2" > Ports [1, 1] > Position [2620, 184, 2675, 206] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out3" > Ports [1, 1] > Position [2620, 54, 2675, 76] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out4" > Ports [1, 1] > Position [2620, 249, 2675, 271] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Mux" > Ports [9, 1] > Position [2285, 314, 2345, 686] > SourceBlock "xbsIndex_r3/Mux" > SourceType "Xilinx Multiplexer Block" > inputs "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "on" > mux_type "off" > use_rpm "off" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Mux1" > Ports [9, 1] > Position [2285, 744, 2345, 1116] > SourceBlock "xbsIndex_r3/Mux" > SourceType "Xilinx Multiplexer Block" > inputs "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > mux_type "off" > use_rpm "off" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Mux2" > Ports [9, 1] > Position [2285, 1179, 2345, 1551] > SourceBlock "xbsIndex_r3/Mux" > SourceType "Xilinx Multiplexer Block" > inputs "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > mux_type "off" > use_rpm "off" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Mux3" > Ports [9, 1] > Position [2285, 1614, 2345, 1986] > SourceBlock "xbsIndex_r3/Mux" > SourceType "Xilinx Multiplexer Block" > inputs "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > mux_type "off" > use_rpm "off" > gen_core "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "SEL_HI" > Ports [4, 1] > Position [1315, 455, 1360, 630] > SourceBlock "xbsIndex_r3/Logical" > SourceType "Xilinx Logical Block" > logical_function "OR" > inputs "4" > precision "Full" > arith_type "Unsigned" > n_bits "8" > bin_pt "2" > align_bp "on" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "SEL_LO" > Ports [4, 1] > Position [1315, 45, 1360, 220] > SourceBlock "xbsIndex_r3/Logical" > SourceType "Xilinx Logical Block" > logical_function "OR" > inputs "4" > precision "Full" > arith_type "Unsigned" > n_bits "8" > bin_pt "2" > align_bp "on" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "SEL_MID" > Ports [4, 1] > Position [1315, 250, 1360, 425] > SourceBlock "xbsIndex_r3/Logical" > SourceType "Xilinx Logical Block" > logical_function "OR" > inputs "4" > precision "Full" > arith_type "Unsigned" > n_bits "8" > bin_pt "2" > align_bp "on" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Scope > Name "Scope" > Ports [1] > Position [2105, 189, 2135, 221] > Location [188, 390, 512, 629] > Open off > NumInputPorts "1" > List { > ListType AxesTitles > axes1 "%<SignalLabel>" > } > DataFormat "StructureWithTime" > } > Block { > BlockType Scope > Name "Scope1" > Ports [4] > Position [2745, 27, 2870, 298] > Location [313, 130, 1473, 924] > Open off > NumInputPorts "4" > ZoomMode "yonly" > List { > ListType AxesTitles > axes1 "%<SignalLabel>" > axes2 "%<SignalLabel>" > axes3 "%<SignalLabel>" > axes4 "%<SignalLabel>" > } > YMin "-5~-5~-5~-5" > YMax "5~5~5~5" > SaveName "ScopeData1" > DataFormat "StructureWithTime" > LimitDataPoints off > } > Block { > BlockType Reference > Name "Shift" > Ports [1, 1] > Position [2115, 366, 2160, 394] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "3" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift1" > Ports [1, 1] > Position [2115, 646, 2160, 674] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "10" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift10" > Ports [1, 1] > Position [2115, 836, 2160, 864] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "4" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift11" > Ports [1, 1] > Position [2115, 876, 2160, 904] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "5" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift12" > Ports [1, 1] > Position [2115, 916, 2160, 944] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "6" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift13" > Ports [1, 1] > Position [2115, 956, 2160, 984] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "7" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift14" > Ports [1, 1] > Position [2115, 996, 2160, 1024] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift15" > Ports [1, 1] > Position [2115, 1036, 2160, 1064] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "9" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift16" > Ports [1, 1] > Position [2115, 1231, 2160, 1259] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "3" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift17" > Ports [1, 1] > Position [2115, 1511, 2160, 1539] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "10" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift18" > Ports [1, 1] > Position [2115, 1706, 2160, 1734] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "4" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift19" > Ports [1, 1] > Position [2115, 1746, 2160, 1774] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "5" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift2" > Ports [1, 1] > Position [2115, 796, 2160, 824] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "3" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift20" > Ports [1, 1] > Position [2115, 1786, 2160, 1814] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "6" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift21" > Ports [1, 1] > Position [2115, 1826, 2160, 1854] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "7" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift22" > Ports [1, 1] > Position [2115, 1866, 2160, 1894] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift23" > Ports [1, 1] > Position [2115, 1906, 2160, 1934] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "9" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift24" > Ports [1, 1] > Position [2115, 1666, 2160, 1694] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "3" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift25" > Ports [1, 1] > Position [2115, 1271, 2160, 1299] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "4" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift26" > Ports [1, 1] > Position [2115, 1311, 2160, 1339] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "5" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift27" > Ports [1, 1] > Position [2115, 1351, 2160, 1379] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "6" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift28" > Ports [1, 1] > Position [2115, 1391, 2160, 1419] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "7" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift29" > Ports [1, 1] > Position [2115, 1431, 2160, 1459] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift3" > Ports [1, 1] > Position [2115, 406, 2160, 434] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "4" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift30" > Ports [1, 1] > Position [2115, 1471, 2160, 1499] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "9" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift31" > Ports [1, 1] > Position [2115, 1946, 2160, 1974] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "10" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift4" > Ports [1, 1] > Position [2115, 446, 2160, 474] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "5" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift5" > Ports [1, 1] > Position [2115, 486, 2160, 514] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "6" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift6" > Ports [1, 1] > Position [2115, 526, 2160, 554] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "7" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift7" > Ports [1, 1] > Position [2115, 566, 2160, 594] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "8" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift8" > Ports [1, 1] > Position [2115, 606, 2160, 634] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "9" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Shift9" > Ports [1, 1] > Position [2115, 1076, 2160, 1104] > ShowName off > SourceBlock "xbsIndex_r3/Shift" > SourceType "Xilinx Shift Block" > shift_dir "Right" > shift_bits "10" > precision "Full" > arith_type "Signed (2's comp)" > n_bits "8" > bin_pt "2" > quantization "Truncate" > overflow "Wrap" > latency "0" > explicit_period "off" > period "1" > en "off" > dbl_ovrd "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Slice10" > Ports [1, 1] > Position [675, 76, 720, 104] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "1" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice11" > Ports [1, 1] > Position [675, 121, 720, 149] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "2" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice12" > Ports [1, 1] > Position [675, 176, 720, 204] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "3" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice13" > Ports [1, 1] > Position [675, 221, 720, 249] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "4" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice14" > Ports [1, 1] > Position [675, 276, 720, 304] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "5" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice15" > Ports [1, 1] > Position [675, 321, 720, 349] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "6" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice16" > Ports [1, 1] > Position [675, 371, 720, 399] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "1" > bit1 "0" > base1 "MSB of Input" > bit0 "7" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Reference > Name "Slice8" > Ports [1, 1] > Position [525, 76, 570, 104] > ShowName off > SourceBlock "xbsIndex_r3/Slice" > SourceType "Xilinx Slice Block" > mode "Lower Bit Location + Width" > nbits "8" > bit1 "0" > base1 "MSB of Input" > bit0 "3" > base0 "LSB of Input" > boolean_output "off" > explicit_period "off" > period "1" > dbl_ovrd "off" > } > Block { > BlockType Outport > Name "Out1" > Position [3000, 493, 3030, 507] > IconDisplay "Port number" > BusOutputAsStruct off > } > Block { > BlockType Outport > Name "Out2" > Position [3000, 923, 3030, 937] > Port "2" > IconDisplay "Port number" > BusOutputAsStruct off > } > Block { > BlockType Outport > Name "Out3" > Position [3000, 1358, 3030, 1372] > Port "3" > IconDisplay "Port number" > BusOutputAsStruct off > } > Block { > BlockType Outport > Name "Out4" > Position [3000, 1793, 3030, 1807] > Port "4" > IconDisplay "Port number" > BusOutputAsStruct off > } > Line { > SrcBlock "AddSub6" > SrcPort 1 > DstBlock "Slice8" > DstPort 1 > } > Line { > SrcBlock "Mux" > SrcPort 1 > Points [0, 0; 150, 0] > Branch { > DstBlock "Out1" > DstPort 1 > } > Branch { > Points [0, -435] > DstBlock "Gateway Out3" > DstPort 1 > } > } > Line { > SrcBlock "Shift" > SrcPort 1 > DstBlock "Mux" > DstPort 2 > } > Line { > SrcBlock "Shift3" > SrcPort 1 > DstBlock "Mux" > DstPort 3 > } > Line { > SrcBlock "Shift4" > SrcPort 1 > DstBlock "Mux" > DstPort 4 > } > Line { > SrcBlock "Shift5" > SrcPort 1 > DstBlock "Mux" > DstPort 5 > } > Line { > SrcBlock "Shift6" > SrcPort 1 > DstBlock "Mux" > DstPort 6 > } > Line { > SrcBlock "Shift7" > SrcPort 1 > DstBlock "Mux" > DstPort 7 > } > Line { > SrcBlock "Shift8" > SrcPort 1 > DstBlock "Mux" > DstPort 8 > } > Line { > SrcBlock "Shift1" > SrcPort 1 > DstBlock "Mux" > DstPort 9 > } > Line { > SrcBlock "Constant1" > SrcPort 1 > DstBlock "AddSub6" > DstPort 1 > } > Line { > SrcBlock "Shift2" > SrcPort 1 > DstBlock "Mux1" > DstPort 2 > } > Line { > SrcBlock "Shift10" > SrcPort 1 > DstBlock "Mux1" > DstPort 3 > } > Line { > SrcBlock "Shift11" > SrcPort 1 > DstBlock "Mux1" > DstPort 4 > } > Line { > SrcBlock "Shift12" > SrcPort 1 > DstBlock "Mux1" > DstPort 5 > } > Line { > SrcBlock "Shift13" > SrcPort 1 > DstBlock "Mux1" > DstPort 6 > } > Line { > SrcBlock "Shift14" > SrcPort 1 > DstBlock "Mux1" > DstPort 7 > } > Line { > SrcBlock "Shift15" > SrcPort 1 > DstBlock "Mux1" > DstPort 8 > } > Line { > SrcBlock "Shift9" > SrcPort 1 > DstBlock "Mux1" > DstPort 9 > } > Line { > SrcBlock "Shift16" > SrcPort 1 > DstBlock "Mux2" > DstPort 2 > } > Line { > SrcBlock "Shift25" > SrcPort 1 > DstBlock "Mux2" > DstPort 3 > } > Line { > SrcBlock "Shift26" > SrcPort 1 > DstBlock "Mux2" > DstPort 4 > } > Line { > SrcBlock "Shift27" > SrcPort 1 > DstBlock "Mux2" > DstPort 5 > } > Line { > SrcBlock "Shift28" > SrcPort 1 > DstBlock "Mux2" > DstPort 6 > } > Line { > SrcBlock "Shift29" > SrcPort 1 > DstBlock "Mux2" > DstPort 7 > } > Line { > SrcBlock "Shift30" > SrcPort 1 > DstBlock "Mux2" > DstPort 8 > } > Line { > SrcBlock "Shift17" > SrcPort 1 > DstBlock "Mux2" > DstPort 9 > } > Line { > SrcBlock "Shift24" > SrcPort 1 > DstBlock "Mux3" > DstPort 2 > } > Line { > SrcBlock "Shift18" > SrcPort 1 > DstBlock "Mux3" > DstPort 3 > } > Line { > SrcBlock "Shift19" > SrcPort 1 > DstBlock "Mux3" > DstPort 4 > } > Line { > SrcBlock "Shift20" > SrcPort 1 > DstBlock "Mux3" > DstPort 5 > } > Line { > SrcBlock "Shift21" > SrcPort 1 > DstBlock "Mux3" > DstPort 6 > } > Line { > SrcBlock "Shift22" > SrcPort 1 > DstBlock "Mux3" > DstPort 7 > } > Line { > SrcBlock "Shift23" > SrcPort 1 > DstBlock "Mux3" > DstPort 8 > } > Line { > SrcBlock "Shift31" > SrcPort 1 > DstBlock "Mux3" > DstPort 9 > } > Line { > SrcBlock "In1" > SrcPort 1 > Points [2020, 0] > Branch { > DstBlock "Shift1" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift8" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift7" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift6" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift5" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift4" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > Points [0, -40] > DstBlock "Shift" > DstPort 1 > } > Branch { > DstBlock "Shift3" > DstPort 1 > } > } > } > } > } > } > } > } > Line { > SrcBlock "Gateway Out" > SrcPort 1 > Points [55, 0] > Branch { > DstBlock "Scope" > DstPort 1 > } > Branch { > Points [0, 60] > DstBlock "Display" > DstPort 1 > } > } > Line { > SrcBlock "Concat" > SrcPort 1 > Points [300, 0] > Branch { > Points [0, -135] > DstBlock "Gateway Out" > DstPort 1 > } > Branch { > Points [320, 0] > Branch { > DstBlock "Mux" > DstPort 1 > } > Branch { > Points [0, 430] > Branch { > DstBlock "Mux1" > DstPort 1 > } > Branch { > Points [0, 435] > Branch { > Points [0, 435] > DstBlock "Mux3" > DstPort 1 > } > Branch { > DstBlock "Mux2" > DstPort 1 > } > } > } > } > } > Line { > SrcBlock "In2" > SrcPort 1 > Points [2020, 0] > Branch { > DstBlock "Shift9" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift15" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift14" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift13" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift12" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift11" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > Points [0, -40] > DstBlock "Shift2" > DstPort 1 > } > Branch { > DstBlock "Shift10" > DstPort 1 > } > } > } > } > } > } > } > } > Line { > SrcBlock "Mux1" > SrcPort 1 > Points [0, 0; 180, 0] > Branch { > DstBlock "Out2" > DstPort 1 > } > Branch { > Points [0, -800] > DstBlock "Gateway Out1" > DstPort 1 > } > } > Line { > SrcBlock "Mux2" > SrcPort 1 > Points [0, 0; 210, 0] > Branch { > DstBlock "Out3" > DstPort 1 > } > Branch { > Points [0, -1170] > DstBlock "Gateway Out2" > DstPort 1 > } > } > Line { > SrcBlock "Mux3" > SrcPort 1 > Points [0, 0; 240, 0] > Branch { > DstBlock "Out4" > DstPort 1 > } > Branch { > Points [0, -1540] > DstBlock "Gateway Out4" > DstPort 1 > } > } > Line { > SrcBlock "Gateway Out3" > SrcPort 1 > DstBlock "Scope1" > DstPort 1 > } > Line { > SrcBlock "Gateway Out1" > SrcPort 1 > DstBlock "Scope1" > DstPort 2 > } > Line { > SrcBlock "Gateway Out2" > SrcPort 1 > DstBlock "Scope1" > DstPort 3 > } > Line { > SrcBlock "Gateway Out4" > SrcPort 1 > DstBlock "Scope1" > DstPort 4 > } > Line { > SrcBlock "In3" > SrcPort 1 > Points [2020, 0] > Branch { > DstBlock "Shift17" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift30" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift29" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift28" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift27" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift26" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > Points [0, -40] > DstBlock "Shift16" > DstPort 1 > } > Branch { > DstBlock "Shift25" > DstPort 1 > } > } > } > } > } > } > } > } > Line { > SrcBlock "acc_len_val" > SrcPort 1 > DstBlock "AddSub6" > DstPort 2 > } > Line { > SrcBlock "In4" > SrcPort 1 > Points [2020, 0] > Branch { > DstBlock "Shift31" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift23" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift22" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift21" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift20" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > DstBlock "Shift19" > DstPort 1 > } > Branch { > Points [0, -40] > Branch { > Points [0, -40] > DstBlock "Shift24" > DstPort 1 > } > Branch { > DstBlock "Shift18" > DstPort 1 > } > } > } > } > } > } > } > } > Line { > SrcBlock "Slice8" > SrcPort 1 > Points [60, 0] > Branch { > DstBlock "Slice10" > DstPort 1 > } > Branch { > Points [0, 45] > Branch { > DstBlock "Slice11" > DstPort 1 > } > Branch { > Points [0, 55] > Branch { > DstBlock "Slice12" > DstPort 1 > } > Branch { > Points [0, 45] > Branch { > DstBlock "Slice13" > DstPort 1 > } > Branch { > Points [0, 55] > Branch { > DstBlock "Slice14" > DstPort 1 > } > Branch { > Points [0, 45] > Branch { > Points [0, 50] > DstBlock "Slice16" > DstPort 1 > } > Branch { > DstBlock "Slice15" > DstPort 1 > } > } > } > } > } > } > } > Line { > SrcBlock "Slice16" > SrcPort 1 > Points [0, 0; 85, 0] > Branch { > Points [0, 225] > DstBlock "SEL_HI" > DstPort 4 > } > Branch { > Points [175, 0] > Branch { > Points [0, -185] > DstBlock "SEL_LO" > DstPort 4 > } > Branch { > Points [0, 20] > DstBlock "SEL_MID" > DstPort 4 > } > } > } > Line { > SrcBlock "Slice15" > SrcPort 1 > Points [0, 0; 240, 0] > Branch { > Points [0, -180] > DstBlock "SEL_LO" > DstPort 3 > } > Branch { > Points [0, 25] > DstBlock "SEL_MID" > DstPort 3 > } > } > Line { > SrcBlock "Slice14" > SrcPort 1 > Points [0, 0; 105, 0] > Branch { > Points [115, 0; 0, -180] > DstBlock "SEL_LO" > DstPort 2 > } > Branch { > Points [0, 275] > DstBlock "SEL_HI" > DstPort 3 > } > } > Line { > SrcBlock "Slice13" > SrcPort 1 > Points [200, 0; 0, -170] > DstBlock "SEL_LO" > DstPort 1 > } > Line { > SrcBlock "Slice10" > SrcPort 1 > Points [145, 0; 0, 385] > DstBlock "SEL_HI" > DstPort 1 > } > Line { > SrcBlock "Slice12" > SrcPort 1 > Points [125, 0; 0, 125] > Branch { > Points [0, 205] > DstBlock "SEL_HI" > DstPort 2 > } > Branch { > DstBlock "SEL_MID" > DstPort 2 > } > } > Line { > SrcBlock "Slice11" > SrcPort 1 > Points [435, 0; 0, 135] > DstBlock "SEL_MID" > DstPort 1 > } > Line { > SrcBlock "SEL_LO" > SrcPort 1 > Points [95, 0; 0, 145] > DstBlock "Concat" > DstPort 1 > } > Line { > SrcBlock "SEL_MID" > SrcPort 1 > DstBlock "Concat" > DstPort 2 > } > Line { > SrcBlock "SEL_HI" > SrcPort 1 > Points [95, 0; 0, -145] > DstBlock "Concat" > DstPort 3 > } > } > } > Block { > BlockType Reference > Name "Gateway Out" > Ports [1, 1] > Position [1740, 239, 1795, 261] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out1" > Ports [1, 1] > Position [1740, 204, 1795, 226] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out10" > Ports [1, 1] > Position [1745, 939, 1800, 961] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out11" > Ports [1, 1] > Position [1745, 904, 1800, 926] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out12" > Ports [1, 1] > Position [1745, 1009, 1800, 1031] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out13" > Ports [1, 1] > Position [1745, 974, 1800, 996] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out14" > Ports [1, 1] > Position [1740, 274, 1795, 296] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out15" > Ports [1, 1] > Position [1055, 89, 1110, 111] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out16" > Ports [1, 1] > Position [1055, 54, 1110, 76] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out17" > Ports [1, 1] > Position [1055, 159, 1110, 181] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out18" > Ports [1, 1] > Position [1055, 124, 1110, 146] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out19" > Ports [1, 1] > Position [1740, 309, 1795, 331] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out2" > Ports [1, 1] > Position [1295, 94, 1350, 116] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out3" > Ports [1, 1] > Position [1295, 59, 1350, 81] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt "6" > arith_type "Boolean" > quantization "Truncate" > overflow "Wrap" > hdl_port "on" > timing_constraint "None" > locs_specified "off" > LOCs "{}" > needs_fixed_name "off" > show_param "off" > xl_area "[0, 0, 0, 0, 0, 0, 0]" > xl_use_area "off" > } > Block { > BlockType Reference > Name "Gateway Out4" > Ports [1, 1] > Position [1295, 164, 1350, 186] > ShowName off > SourceBlock "xbsIndex_r3/Gateway Out" > SourceType "Xilinx Gateway Out" > output_type "Double" > nbits "8" > bin_pt >
