Hi list,
I derived new library and pcore components for the ADC block. I'd hope to
get the 1:2 demuxed ADC block included in Casper. It could be useful for
several people.
The goal was to make fs=1024 MHz 2-channel sampling possible in more
complex designs that now run IP from adc0_clk at fs/8=128M instead
of fs/4=256M.
Essentially I regenerated the FIFO from 72:72-bit to 72:144-bit 32-depth,
added a second copy of the DCM with CLKIN_DIVIDE_BY_2 set True, 'and'
together the DCM's LOCKED into ctrl_dcm_locked, and output
ctrl_clk(90)_out.
The UCF has a new entry
# 1024 MHz/8 = 128 MHz : 7.8125ns
NET adc0_clk TNM_NET = adc0_clk;
TIMESPEC TS_adc0_clk = PERIOD adc0_clk 7800ps ;
Well of course, there is a problem :-)
Occasionally, after the design has run for some time (some seconds to
minutes), the FIFO 'valid' output becomes stuck at 0. The rest of the
design continues to work fine.
The timing analysis would say all is ok, and the xflow output log IMHO
would indicate it too:
http://www.metsahovi.fi/~jwagner/iBob/toolchain/xps_lib/pcores/adc2demuxed-interface-xflow.log
I'm not sure if this is a DCM setup problem? Currently the second DCM is
fed from buffered adc_lk.
It might also be the FIFO itself. Do you know if an async FIFO with
aspect ratio other than 1:1 can't run at equally high frequencies as a
1:1 FIFO?
The VHDL is over here.
I'd appreciate if someone could take a look!
http://www.metsahovi.fi/~jwagner/iBob/toolchain/xps_lib/pcores/adc2demuxed_interface_v1_00_a/hdl/vhdl/adc2demuxed_interface.vhd
Many thanks in advance,
- Jan
--
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Helsinki University of Technology
Dept. of Metsähovi Radio Observatory
http://www.metsahovi.fi/~jwagner/
Work +358-9-256-4424
