Hi Glenn,
Do you have the "pack register into IOB" option checked for the LED?
I haven't confirmed, but I believe that there is some IOB sharing
going on with the DIMMs and GPIOs. If that option is on, then it
would explain the error, as the IOB pair would be trying to use
different clocks. Turning off the option would let output registering
for the LED be pulled out of the IOB, so the clock conflict can be
resolved.
Thanks,
Henry
Jason Manley wrote:
I have never seen this before, and I am using all the user LEDs and
DIMM1 and DIMM2 in the correlator design.
On 10 Jul 2008, at 00:15, G Jones wrote:
Hello,
I am trying to route a design using DRAM and BEE2_usr:led GPIO and I
ran into the following PAR error:
ERROR:Place:17 - The placement constraints of the IOBs dimm2_dqs<2> and
drambuffer_impl_gpio_ext<5> makes this design unroutable due to a
physical
routing limitation. This device has a shared routing resource
connecting the
ICLK and OTCLK pins on pairs of IOBs. This restriction means that
these
pairs of pins must be driven by the same signal or one of the
signals will be
unroutable. Before continuing please remove the placement
constraints or
move one of these IOBs to a new location.
ERROR:MDT - :Place:17 - The placement constraints of the IOBs
dimm2_dqs<1> and
drambuffer_impl_gpio_ext<4> makes this design unroutable due to a
physical
routing limitation. This device has a shared routing resource
connecting
the
ICLK and OTCLK pins on pairs of IOBs. This restriction means
that these
pairs of pins must be driven by the same signal or one of the
signals will
be
unroutable. Before continuing please remove the placement
constraints or
move one of these IOBs to a new location.
I found this answer from Xilinx:
http://www.xilinx.com/support/answers/18780.htm
I don't really understand the error, so I am wondering if I should set
the environment variable as suggested, or if there is actually a
conflict in the DRAM and GPIO pins
Thanks,
Glenn
