Greg,
Perhaps a CASPER maintainer can correct me if I'm wrong, but I believe I am
using the black box, because the files used are .ngo files. There is also a
"black box definition" bbd file. The pcore is called ddr2_controller_v2_00_a
if that helps any.
Thanks,
Glenn

On Mon, Sep 8, 2008 at 7:29 AM, Greg Gibeling <[email protected]> wrote:

>        Am I missing something here?  Are you synthesizing the memory
> controller from source?  Or are you using the black box?
>
> -Greg
>
> > -----Original Message-----
> > From: [email protected] [mailto:bee2-users-
> > [email protected]] On Behalf Of G Jones
> > Sent: Monday, September 08, 2008 1:22 AM
> > To: BEE2 Users
> > Subject: [bee2-users] Difficulty meeting timing with DRAM in ISE 10.1
> >
> > Hello, I am cross posting this to the bee2-users list in case anyone
> knows
> > more about the DRAM controller for the BEE2. I'm not sure if the version
> > used by CASPER is outdated, but I appreciate any insight.
> > Thank you,
> > Glenn
> >
> >
> > ---------- Forwarded message ----------
> > From: G Jones <[email protected]>
> > Date: Fri, Sep 5, 2008 at 11:53 PM
> > Subject: Difficulty meeting timing with DRAM in 10.1
> > To: [email protected]
> >
> >
> >
> > Hello,
> > I am migrating my designs from ISE 7.1 to 10.1 and have run into trouble
> > meeting timing for designs using DRAM which previously met timing in 7.1.
> > Specifically, all of the failing constraints have the following form.
> > * NET         "ddr2_controller_1/ddr2_contr | MAXDELAY|    -0.209ns|
> > 0.266ns|       1|         209
> >   oller_1/data_path0/data_read_controller0/ |         |            |
> > |        |
> >   dqs_delay1_col1/delay1"         MAXDELAY  |         |            |
> > |        |
> >   = 0.057 ns                                |         |            |
> > |        |
> >
> > 36 such constraints are failing in exactly the same way, but some of the
> > 0.057 ns constraints succeed.
> > I am trying to clock the DRAM at 200 MHz and the system off sys_clk2x =
> > 200 MHz, so nothing too extreme.
> > I wonder if the timing models became more conservative between 7.1 and
> > 10.1? One noticable difference is in 7.1 the voltage was initialized to
> > 1.5 V but in 10.1 it's at 1.4 V.
> >
> > I appreciate any pointers on this problem.
> > Thanks,
> > Glenn
> >
>
>
>
>

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