You might take a look at the counters that go into the look-up tables that generate the sine/cosine LOs. I have a feeling that these counters might not have resets, causing the two counters to come up at random times relative to one another, shifting the phases of the sin/cos and thus the real/imag components. This could be fixed by propagating a sync into these counters.
On Wed, Sep 24, 2008 at 1:44 AM, G Jones <[email protected]> wrote: > Hi everyone, > I just spent a long time struggling with this problem, so I wanted to warn > others in case you run into it. > It seems that the 10.1 DDC blocks simulate fine in simulink, but something > goes wrong when building the design. The major symptom is that the filter > does not have the expected rejection characteristics, and more importantly, > the real and imaginary outputs are not in quadrature for a single tone in > the passband, as they should be. Again, in simulation things look fine. I > even recorded actual ADC data and fed it into the simulation and the output > was exactly what I expected, but in hardware I kept getting a mirrored > spectrum. Finally I captured the output of the DDC block and saw that the > real and imaginary components are generally 180 degrees out of phase. After > building several iterations of the design, I finally decided to give 7.1 a > shot and it came out perfectly the first time. > I am using the blocks with the LO set at 1 and decimating 4 simultaneous ADC > inputs down to 1 complex output. > Please let me know if you've seen a problem like this and have an idea as to > where to start looking to fix it. I seached the map output to see if > anything obvious was being optimized out but didn't find anything. > > Hope this helps someone, > Glenn > -- Aaron Parsons 510-406-4322 (cell) 787-878-2612 x329 (arecibo office) 787-721-3991 (home)
