Hi all. Here's a timing error that appears when building a large (2^^3 parallel paths, 2^^13 points, 4 taps 7 bit coefficients, 7 bit input, 14 bit output) PFB. The timing wizard's suggestions are below. Note that the coeff. generator counter seems to be used for all coeff generator counters in the entire PFB's complement of coeff generators.
How can I tell the toolset not to optimize out all the other counters, or alternatively, how can I introduce a delay to fix this problem? I've attached the twx file, but from the timing wizard: This path has a net "b2_gdsp_u1_8k_800_a_nb_xsg_core_config/b2_gdsp_u1_8k_800_a_nb_xsg_core_config/ top/pfb_fir_real_4k_ch/pol1_in1_first_tap/pfb_coeff_gen/counter_q(4)" with a high fanout of 450. High fanout suggestions. -Duplicate the net source and direct the synthesis tools not to remove duplicate logic. -Use a specific net fanout control on the problem net if allowed by the synthesis tool. Click Next button if this suggestion does not help. Thanks for any help! John
