Hi Laura, Weird. This is from a real sin wave in a running design? Does i2/i4 stay stuck at 32 when you change the amplitude/frequency of the input?
- Andrew On 12/7/08 3:49 PM, "Laura Spitler" <[email protected]> wrote: > Hi everyone, > > I'm seeing some strange behavior in the ADC block in 10.1 that's part of a DDC > design I'm working on. The board is the "classic" iADC (ADC2x1000-8). The > input clock 400 MHz, the iBOB is running at 100 MHz and interleave mode is > turned off. I put a SNAP block directly on the output of the ADC by > concatenating the four 8-bit samples. > The output traces a sine wave except that samples i2 and i4 are a constant, > namely 32 for the I input and about 66 for the Q input when I changed my model > to get data second input. I've done several captures, and it's always the same > value and always i2 and i4. I don't think it's an issue with the snapshot > because looking at the output of the mixer also shows that the second and > fourth data streams are constant. > Could this be an issue with demultiplexing in the ADC? > > Glenn, several months ago you mentioned that you were having trouble with the > DDC in 10.1 and captured data ADC from the ADC directly. Did you see this > problem with i2 and i4? (And btw, I'm also getting the strange mirrored > output, but that'll probably be another email.) > > Here are a couple lines of my data (first column is sample number; ignore the > columns with zeros; column 4 is the signed version of column 2): > > 0 47 0 47 0 > 1 32 0 32 0 > 2 45 0 45 0 > 3 32 0 32 0 > 4 43 0 43 0 > 5 32 0 32 0 > 6 38 0 38 0 > 7 32 0 32 0 > 8 32 0 32 0 > 9 32 0 32 0 > 10 26 0 26 0 > 11 32 0 32 0 > 12 18 0 18 0 > 13 32 0 32 0 > 14 9 0 9 0 > 15 32 0 32 0 > 16 0 0 0 0 > 17 32 0 32 0 > 18 247 0 -9 0 > 19 32 0 32 0 > 20 239 0 -17 0 > > > Thanks! > Laura >
