Hi, Glenn,
We've done something similar on the ATA DDC, though it's 4 reals down
to 1 complex per clock cycle. The technique for 8 reals down to 2
complex would be similar.
We used one Xilinx FIR filter block on each of the 4 input
"legs" (L=4), but any streaming FIR filter should work. The
coefficients of each the L FIR filters are the L-way polyphase
decomposition of the coefficients of the larger filter.
We use a fixed LO of Fs/4, so the LO values are +1, -j. -1, +j, which
means that the LO for each leg is fixed at +/- 1 or +/- j so we
simply feed the FIR filters outputs into two subtract blocks (one for
real and one for imaginary) as appropriate. If you are OK with a
fixed LO of Fs/4 (i.e. with the 500 MHz band centered at 500 MHz),
then you could do the same, though you'd have two +1 legs, two -j
legs, etc. to sum/diff.
Hope this helps,
Dave
On Apr 6, 2009, at 10:20 , G Jones wrote:
Hello,
Has anyone made a decimating FIR filter that outputs two samples
per clock instead of just one as the block in the CASPER library
does? Specifically I'd like to use the interleaved ADC at 2 Gsps
and then filter the 8 real samples at a time down to 2 complex
samples representing 1/2 of the band (500 MHz). The block in the
CASPER library will let me filter the 8 real samples down to 1
complex sample representing 1/4 of the band. If no one else has
done this, I will go ahead and try to make such a block.
Thanks,
Glenn
