Hi, Randy,
We have this same situation times 8 at the ATA (i.e. 16 ibobs). We
do not try to lock the ibob clocks together. Instead we re-calibrate
the system's fixed delays every time the ibobs are power cycled (or
otherwise reset). While this is not convenient the ibobs do have
very good uptimes (currently 75 days and counting!) so it is not a
frequent operation.
I do not know of a way to synchronize the ADC output clocks across
multiple ibobs.
Dave
On Jul 20, 2009, at 14:27 , Randy McCullough wrote:
Our application calls for two iBOBS, each with one 1.6 GSPS ADC, to
coherently sample two separate sample streams which represent our
polarization 0 and polarization 1 inputs.
Our ADCs are set up for 800 MHz (interlaced); while our iBOB logic
clocks are set up to run at 200 MHz (Tp = 5nSEC). Given the 4X ratio
between the ADC clocks and the logic clocks, there is an N x (5nSEC)/4
uncertainty in the relative phase of the two iBOB logic clocks at
power up.
This appears to be a natural consequence of the random nature of
the power
up timing of the two iBOBs, and which 800 MHz cycle they choose to
"lock"
to (Both ADCs are tied directly to the same 800 MHz sampling clock
with
matched cabling, etc.)
Does anyone know of a way to guarantee phase coherence between two
iBOB logic clocks under such a scenario?
Thanks,
Randy
