Hello David, I haven't update my mlib 10.1 for 2 months. This must be the reason. I'll update my svn and re-compile my design. Meanwhile I'll manually adjust the clock phase to see if I can fix the problem. Thanks for the help.
Best Regards, Zhiwei On Thu, Aug 13, 2009 at 2:48 AM, David George <[email protected]>wrote: > Hello Zhiwei. > >> Does anyone have the similar problem? Or is there anyone have ever run the >> roach design with FPGA clock larger than 250 MHz. >> > I have build spectrometers up to 256 Mhz. However, I encountered a similar > problem with my spectrometer design. The problem turned out to be that the > adc clock was by default out of phase by 90 degress with respect to the adc > data lines. This was fixed in the mlib 10.1 tools about a month ago, have > you updated your svn recently? > > You can manually adjust the clock phase on your current design by > manipulating the adc controller registers in borph or uboot. You need to > write to the adc controller with an offset of 3 with the following: > * 0x03 increment adc0 phase by one step > * 0x02 decrement adc0 phase by one step > * 0x30 increment adc1 phase by one step > * 0x20 decrement adc1 phase by one step > > For instance from borph: echo -e -n "\0\0\0003\0" > my_adc_register. 64 > phase steps corresponds to 90 degrees (If I remember correctly). A good way > to analyse this is to look at the time domain signals. I hope this helps. > > Regards, > David > > - > > David George > Digital Design Engineer > Karoo Array Telescope > Tel: +27 21 531-7282 > Fax: +27 21 531-9761 > Email: [email protected] > Web: www.ska.ac.za > > -- Zhiwei Liu
