Hi All, The fifo errors:
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC... ERROR:MDT - :sim:52 - Could not find selected IP. ERROR:MDT - ERROR FROM TCL:- resun_v1_1_DATAFIFO (opb_asyncfifo_simulink2ppc)... were eventually resolved by installing Xilinx's 7.1i IP Update #3 (had to use the manual update option, as automatic update form the coregen gui didn't work). See: http://www.xilinx.com/support/answers/21938.htm Thanks Henry! - Andrew On 8/31/09 3:47 PM, "William Mallard" <[email protected]> wrote: > Ted Jaeger wrote: >> William Mallard wrote: >>> Ted Jaeger wrote: >>>> Is there a tutorial anywhere on setting up the software needed for a >>>> fully functional iBOB development system. I have been following the >>>> wiki articles on the required software and how to add the MSSGE tool >>>> flow, but I (and maybe other introductory users) could use a more >>>> verbose set of instructions. >>> >>> Afaik, the MSSGE Toolflow wiki page is the closest thing we have at >>> the moment. >>> >>> I've been noticing gaps in our documentation lately, and i've been >>> trying to fill them in as i see themq. If you could work out these >>> problems on-list, that would help with the documentation process. >>> >>>> I have full licenses for the Xilinx v7.1 System Generator, ISE and >>>> EDK packages, yet still am generating errors using the FIFO blocks >>>> and seem to be missing the license to use the "opb_ethernetlite" >>>> core. >>> >>> What specific errors are you seeing with the FIFO blocks? >> > ... >> As for the FIFO blocks, I can't seem to get them to compile. I have >> a simple design that samples with an ADC, reads a threshold value >> from a register, then sends triggered samples to a FIFO block to >> temporally store them before they are sent to a host PC via UDP >> packets. > ... >> anything I try to do with FIFO blocks errors out. The design works >> with BRAM blocks, but I'd like to keep using the FIFOs for their >> level/full indicators (they are helpful to tell me if I am sampling >> too fast). > > I've also had bad luck with FIFOs. I eventually gave up and switched > to a scheme that uses BRAMs instead. I'm using snap blocks to readout > data from the design i'm currently working on. > >> I believe the error originates at the output line: >> ERROR FROM TCL (opb_asyncfifo_simulink2ppc) > > This is over my head, but there must be someone on this list who knows > more about yellow blocks. > >> I am missing the xilinx core license for ethernetlite and am not able >> to compile anything with the LWIP block in place. Are the FIFO >> errors related to this? > > Seems unlikely, but it's possible. > > Can you cut-and-paste the errors that you're getting? > > Billy >
