Hi Randy, This is partially written up at:
http://casper.berkeley.edu/wiki/Dram But I'll mention a few highlights. The bursting nature of the DRAM means that each transaction covers 288 bits of data, handled at 2 chunks of 144 bits going into the controller (72 bits in 4 clock edges physically going to the DIMM). So when you are writing to DRAM, you actually need to issue 2 write commands consecutively, but the 2nd address will be ignored. It's important to note that the lowest 3 bits of address are ignored by the memory controller, as they cover subsets in the same 144-bit word location. So to write consecutive 144-bit words into DRAM, you need to: - Hold RNW to '0' - Hold CMD_VALID to '1' - Increment your data word every clock cycle - Increment your address counter by 16 every clock cycle - (Optional) increment CMD_TAG every other clock cycle The definitive document on how to use DRAM, written by the block authors, is actually on the defunct BEE2 wiki. I'll link to it for now, and will transfer the info to the CASPER wiki: http://bee2.eecs.berkeley.edu/wiki/Bee2Memory.html What's important is just the bottom portion covering "User Memory Interface"; the info at the top talks about the raw memory controller interface, which is another layer of abstraction down. Thanks, Henry Randy McCullough wrote:
Can someone explain how to write to and read from bee2 DRAM? I have a simple model which attempts to write numeric values of 0 through 255 into 256 locations, then read these values back and capture them in BRAMS so that "bramdump" can be used to look at the contents. When I run this design in a bee2 USER FPGA, the resultant data out of the DRAM is simply flat-lined as all zeros. Randy
