Hi Terry, I came across something like this before... it almost looks like 11.3 is doing too good of a job of reducing the map logic to wires, because it looks like it's optimizing away the wires. I haven't found a solution, but maybe this is something Xilinx would be able to fix. I think a test case of just a ROM implemented in distributed memory with zero latency and the initial values set to a map that can be reduced to wires should reproduce the problem, but I haven't had a chance to try it.
Glenn On Fri, Jan 15, 2010 at 9:32 PM, Terry Filiba <[email protected]> wrote: > I am trying to compile the FFT in 11.3. It keeps erroring out with the > following error in the system.bld file: > > ERROR:NgdBuild:604 - logical block > > 'seti_spec_test2_XSG_core_config/seti_spec_test2_XSG_core_config/seti_spec_te > > st2_x0/fft1_f2da7491ee/fft_biplex0_e6055a0843/biplex_cplx_unscrambler_3564a9d > 5a9/reorder1_9d9749067a/map1/comp4.core_instance4/BU2' with type > 'dmg_42_vx5_0aa0128fa4a908cf_dist_mem_gen_v4_2_xst_1' could not be > resolved. > A pin name misspelling can cause this, a missing edif or ngc file, or the > misspelling of a type name. Symbol > 'dmg_42_vx5_0aa0128fa4a908cf_dist_mem_gen_v4_2_xst_1' is not supported in > target 'virtex5'. > > If I change the reorder's map to block memory this error goes away but that > is not the default setting in the FFT. > > -Terry >
