[casper] IOB conflict between ADCs and GPIO banks

[Billy Mallard]

Hi all,

I'm trying to add some GPIO outputs to a ROACH design that uses two
ADCs, but ISE seems to be having trouble simultaneously routing IOBs
for the ADCs and the GPIO banks.  Has anyone encountered this?

I'm using 7 out of 8 pins on a single bank, all as outputs, and i've
tried each bank (A and B) independently.  The ADCs are the new 3GSps
NatSemi ones.

Billy

==========
Phase 2.7  Design Feasibility Check
ERROR:Place:864 - Incompatible IOB's are locked to the
 same bank 11
 Conflicting IO Standards are:
 IO Standard 1: Name = LVDS_25, VREF = NR, VCCO = 2.50,
 TERM = NONE, DIR = INPUT, DRIVE_STR = NR
 List of locked IOB's:
      adc0dataoddi_n<4>
      adc0dataoddi_p<4>
      adc0dataoddq_n<2>
      adc0dataoddq_n<4>
      adc0dataoddq_n<5>
      adc0dataoddq_n<6>
      adc0dataoddq_p<2>
      adc0dataoddq_p<4>
      adc0dataoddq_p<5>
      adc0dataoddq_p<6>
      adc0outofrange_n
      adc0outofrange_p
      adc0dataevenq_n<0>
      adc0dataevenq_n<1>
      adc0dataevenq_n<2>
      adc0dataevenq_p<0>
      adc0dataevenq_p<1>
      adc0dataevenq_p<2>
      adc0sync_n
      adc0sync_p

 IO Standard 2: Name = LVCMOS15, VREF = NR, VCCO = 1.50,
 TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
 List of locked IOB's:
      isi_correlator_gpioa_pin0_ext<0>
      isi_correlator_gpioa_pin1_ext<0>
      isi_correlator_gpioa_pin2_ext<0>
      isi_correlator_gpioa_pin3_ext<0>
      isi_correlator_gpioa_pin4_ext<0>
      isi_correlator_gpioa_pin5_ext<0>
      isi_correlator_gpioa_pin6_ext<0>

 These IO Standards are incompatible due to VCCO mismatch.
 This mismatch can be caused by setting DIFF_TERM = TRUE
 for some IOs locked to the bank
==========