Hi John and all: Update you the status of 5Gsps board development here. I met the same problem as Berkeley had. The system as:
5 Gsps ADC board -> 2048 PFB -> 2048 FFT -> Bbram ->KATCP -> Spectrum on Linux. It was working well if the clocking frequency is slower than 1.1GHz,(FPGA freq. = 1.1/4) input signal from 1MHz to 1.1GHz. Once go up to 1,2 GHz (FPGA freq = 300MHz) clocking, there is noise coming up, but signal still visible. Up to 1.3GHz, the spectrum is completely a mess. Obviously, the FPGA is the bottleneck. 2 solutions will be carried out: 1. New PCB run with 1:2 Dmux on 5Gsps ADC board,i.e. only 4 bits resolution, ISERDES is not needed. 2. Add ISERDES in ADC 5Gsps pcores to slow down the data rate. Sorry, those two solutions is not immediately available homin -- Open WebMail Project (http://openwebmail.org) ---------- Original Message ----------- From: [email protected] To: [email protected] Sent: Fri, 23 Apr 2010 05:20:33 -0700 Subject: casper Digest, Vol 29, Issue 10 > Send casper mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > https://calmail.berkeley.edu/manage/list/listinfo/[email protected] ley.edu > > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of casper digest..." > > Today's Topics: > > 1. 6 GS/s Spectrometer (John Ford) > 2. Re: 6 GS/s Spectrometer (Mark Wagner) > 3. Re: 6 GS/s Spectrometer (Suraj Gowda) > 4. Re: 6 GS/s Spectrometer (Dan Werthimer) > 5. Re: 6 GS/s Spectrometer (Jason Manley) > 6. Re: 6 GS/s Spectrometer (Dan Werthimer) > 7. Re: 6 GS/s Spectrometer (Jason Manley) > 8. Re: 6 GS/s Spectrometer (John Ford) > > ---------------------------------------------------------------------- > > Message: 1 > Date: Thu, 22 Apr 2010 17:12:46 -0400 > From: "John Ford" <[email protected]> > Subject: [casper] 6 GS/s Spectrometer > To: [email protected] > Message-ID: > <[email protected]> > Content-Type: text/plain;charset=iso-8859-1 > > Hi all. > > Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC > boards on a ROACH? I seem to recall someone doing something of the > sort, but I don't recall any details. > > Thanks for any info! > > John > > ------------------------------ > > Message: 2 > Date: Thu, 22 Apr 2010 14:57:25 -0700 > From: Mark Wagner <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: John Ford <[email protected]> > Cc: [email protected] > Message-ID: > <[email protected]> > Content-Type: text/plain; charset="iso-8859-1" > > Hi John, > > I don't think anyone has been able to get a spectrometer working at > the full 3GS/s interleaved yet. The best Suraj and I have been able > to do is about > 2.4Gs/s before we start running into serious timing issues. We do have > plans to meet soon with a Xilinx timing expert in the hopes of > resolving our issues. > > Mark > > On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote: > > > Hi all. > > > > Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC > > boards on a ROACH? I seem to recall someone doing something of the sort, > > but I don't recall any details. > > > > Thanks for any info! > > > > John > > > > > > > > > > > -------------- next part -------------- > An HTML attachment scrubbed and removed. > HTML attachments are only available in MIME digests. > > ------------------------------ > > Message: 3 > Date: Thu, 22 Apr 2010 22:23:57 -0700 > From: Suraj Gowda <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: Mark Wagner <[email protected]> > Cc: [email protected] > Message-ID: <[email protected]> > Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes > > Hi John, > > > I don't think anyone has been able to get a spectrometer working at > > the full 3GS/s interleaved yet. > We are able to digitize and plot raw ADC data at full speed. We run > into timing problems when the chip becomes more full, i.e. with an > FFT. One possible solution we are (I am) exploring is pre-routing > the ADC core (as this is where the router fails). If anyone knows > how to pre-route a core for V5 I'd appreciate the help--the Xilinx > documentation isn't all that helpful. > > -Suraj > > ------------------------------ > > Message: 4 > Date: Thu, 22 Apr 2010 22:27:53 -0700 > From: Dan Werthimer <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: John Ford <[email protected]> > Cc: [email protected] > Message-ID: <[email protected]> > Content-Type: text/plain; charset="iso-8859-1" > > hi john, > > we've brought 6Gsps data into the fpga from > a pair of interleaved adc's, with the fpga running at 375 MHz, > and doing small things with it, like storing samples in a buffer, > or doing a short fft. > > but when we add a lot of stuff into the fpga, the fpga no longer > can clock at 375 MHz. > > suraj also developed a yellow block adc which further demuxes > the data so you can bring in 6 Gsps data while > running the fpga at 375/2 MHz, but then there is a very wide > data path, and it takes up a lot of fabric to process this data. > > suraj is planning on hardening the yellow block cores > so that their routing/timing is locked down, independent > of what else is running in the fpga. > > best wishes, > > dan > > On 4/22/2010 2:57 PM, Mark Wagner wrote: > > Hi John, > > > > I don't think anyone has been able to get a spectrometer working at > > the full 3GS/s interleaved yet. The best Suraj and I have been able > > to do is about 2.4Gs/s before we start running into serious timing > > issues. We do have plans to meet soon with a Xilinx timing expert in > > the hopes of resolving our issues. > > > > Mark > > > > > > On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected] > > <mailto:[email protected]>> wrote: > > > > Hi all. > > > > Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC > > boards on a ROACH? I seem to recall someone doing something of > > the sort, > > but I don't recall any details. > > > > Thanks for any info! > > > > John > > > > > > > > > > > > -------------- next part -------------- > An HTML attachment scrubbed and removed. > HTML attachments are only available in MIME digests. > > ------------------------------ > > Message: 5 > Date: Fri, 23 Apr 2010 07:32:31 +0200 > From: Jason Manley <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: Dan Werthimer <[email protected]>, Suraj Gowda > <[email protected]> > Cc: "[email protected] CASPER" <[email protected]> > Message-ID: <[email protected]> > Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes > > > suraj is planning on hardening the yellow block cores > > so that their routing/timing is locked down, independent > > of what else is running in the fpga. > > Please don't make this the default behaviour. On designs that are > nearly fully packed (99%), you need to be able to twiddle every part > of the design to make it fit, and sometimes that means re-arranging > the yellow blocks' innards. Part of the BEE2 DRAM controller was > hard- routed and it caused complications when the chip got full. > > Jason > > > On 4/22/2010 2:57 PM, Mark Wagner wrote: > >> Hi John, > >> > >> I don't think anyone has been able to get a spectrometer working at > >> the full 3GS/s interleaved yet. The best Suraj and I have been > >> able to do is about 2.4Gs/s before we start running into serious > >> timing issues. We do have plans to meet soon with a Xilinx timing > >> expert in the hopes of resolving our issues. > >> > >> Mark > >> > >> > >> On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote: > >> Hi all. > >> > >> Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC > >> boards on a ROACH? I seem to recall someone doing something of the > >> sort, > >> but I don't recall any details. > >> > >> Thanks for any info! > >> > >> John > >> > >> > >> > >> > >> > > > > ------------------------------ > > Message: 6 > Date: Thu, 22 Apr 2010 22:40:11 -0700 > From: Dan Werthimer <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: Jason Manley <[email protected]> > Cc: "[email protected] CASPER" <[email protected]> > Message-ID: <[email protected]> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed > > hi jason, > > perhaps we can have different yellow block cores, > one hardened for people that need high speed input, > one not hardened, > > or better yet - a parameter that selects whether the > routing is hardened or not? > > dan > > On 4/22/2010 10:32 PM, Jason Manley wrote: > >> suraj is planning on hardening the yellow block cores > >> so that their routing/timing is locked down, independent > >> of what else is running in the fpga. > > > > Please don't make this the default behaviour. On designs that are > > nearly fully packed (99%), you need to be able to twiddle every part > > of the design to make it fit, and sometimes that means re-arranging > > the yellow blocks' innards. Part of the BEE2 DRAM controller was > > hard-routed and it caused complications when the chip got full. > > > > Jason > > > >> On 4/22/2010 2:57 PM, Mark Wagner wrote: > >>> Hi John, > >>> > >>> I don't think anyone has been able to get a spectrometer working at > >>> the full 3GS/s interleaved yet. The best Suraj and I have been able > >>> to do is about 2.4Gs/s before we start running into serious timing > >>> issues. We do have plans to meet soon with a Xilinx timing expert > >>> in the hopes of resolving our issues. > >>> > >>> Mark > >>> > >>> > >>> On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote: > >>> Hi all. > >>> > >>> Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC > >>> boards on a ROACH? I seem to recall someone doing something of the > >>> sort, > >>> but I don't recall any details. > >>> > >>> Thanks for any info! > >>> > >>> John > >>> > >>> > >>> > >>> > >>> > >> > > > > ------------------------------ > > Message: 7 > Date: Fri, 23 Apr 2010 07:46:11 +0200 > From: Jason Manley <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: Dan Werthimer <[email protected]> > Cc: "[email protected] CASPER" <[email protected]> > Message-ID: <[email protected]> > Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes > > Yes, I think a parameter is a good idea. Maybe just a radio-box or a > drop-down-selection in the mask. Multiple cores will confuse users > (like everyone gets confused by the multiple FFT blocks) and will > probably become an admin nightmare down the road. > > Jason > > On 23 Apr 2010, at 07:40, Dan Werthimer wrote: > > > > > > > hi jason, > > > > perhaps we can have different yellow block cores, > > one hardened for people that need high speed input, > > one not hardened, > > > > or better yet - a parameter that selects whether the > > routing is hardened or not? > > > > dan > > > > > > > > On 4/22/2010 10:32 PM, Jason Manley wrote: > >>> suraj is planning on hardening the yellow block cores > >>> so that their routing/timing is locked down, independent > >>> of what else is running in the fpga. > >> > >> Please don't make this the default behaviour. On designs that are > >> nearly fully packed (99%), you need to be able to twiddle every > >> part of the design to make it fit, and sometimes that means re- > >> arranging the yellow blocks' innards. Part of the BEE2 DRAM > >> controller was hard-routed and it caused complications when the > >> chip got full. > >> > >> Jason > >> > >>> On 4/22/2010 2:57 PM, Mark Wagner wrote: > >>>> Hi John, > >>>> > >>>> I don't think anyone has been able to get a spectrometer working > >>>> at the full 3GS/s interleaved yet. The best Suraj and I have > >>>> been able to do is about 2.4Gs/s before we start running into > >>>> serious timing issues. We do have plans to meet soon with a > >>>> Xilinx timing expert in the hopes of resolving our issues. > >>>> > >>>> Mark > >>>> > >>>> > >>>> On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote: > >>>> Hi all. > >>>> > >>>> Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s > >>>> ADC > >>>> boards on a ROACH? I seem to recall someone doing something of > >>>> the sort, > >>>> but I don't recall any details. > >>>> > >>>> Thanks for any info! > >>>> > >>>> John > >>>> > >>>> > >>>> > >>>> > >>>> > >>> > >> > > > > ------------------------------ > > Message: 8 > Date: Fri, 23 Apr 2010 08:20:23 -0400 > From: "John Ford" <[email protected]> > Subject: Re: [casper] 6 GS/s Spectrometer > To: "Jason Manley" <[email protected]> > Cc: "[email protected] CASPER" <[email protected]> > Message-ID: > <[email protected]> > Content-Type: text/plain;charset=iso-8859-1 > > Thanks for the info, all. > > As you might expect, this was not an idle question. I have a need > for this right now. The machine I need to build is: > > 3 GHz bandwidth (6 GS/s) > 1024 channels in the spectrometer > 1 polarization > 50 millisecond or less accumulations. > 1 ROACH board > How should we proceed without duplicating effort already underway? How > can we best help bring this to fruition? > > John > > > Yes, I think a parameter is a good idea. Maybe just a radio-box or a > > drop-down-selection in the mask. Multiple cores will confuse users > > (like everyone gets confused by the multiple FFT blocks) and will > > probably become an admin nightmare down the road. > > > > Jason > > > > On 23 Apr 2010, at 07:40, Dan Werthimer wrote: > > > >> > >> > >> hi jason, > >> > >> perhaps we can have different yellow block cores, > >> one hardened for people that need high speed input, > >> one not hardened, > >> > >> or better yet - a parameter that selects whether the > >> routing is hardened or not? > >> > >> dan > >> > >> > >> > >> On 4/22/2010 10:32 PM, Jason Manley wrote: > >>>> suraj is planning on hardening the yellow block cores > >>>> so that their routing/timing is locked down, independent > >>>> of what else is running in the fpga. > >>> > >>> Please don't make this the default behaviour. On designs that are > >>> nearly fully packed (99%), you need to be able to twiddle every > >>> part of the design to make it fit, and sometimes that means re- > >>> arranging the yellow blocks' innards. Part of the BEE2 DRAM > >>> controller was hard-routed and it caused complications when the > >>> chip got full. > >>> > >>> Jason > >>> > >>>> On 4/22/2010 2:57 PM, Mark Wagner wrote: > >>>>> Hi John, > >>>>> > >>>>> I don't think anyone has been able to get a spectrometer working > >>>>> at the full 3GS/s interleaved yet. The best Suraj and I have > >>>>> been able to do is about 2.4Gs/s before we start running into > >>>>> serious timing issues. We do have plans to meet soon with a > >>>>> Xilinx timing expert in the hopes of resolving our issues. > >>>>> > >>>>> Mark > >>>>> > >>>>> > >>>>> On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote: > >>>>> Hi all. > >>>>> > >>>>> Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s > >>>>> ADC > >>>>> boards on a ROACH? I seem to recall someone doing something of > >>>>> the sort, > >>>>> but I don't recall any details. > >>>>> > >>>>> Thanks for any info! > >>>>> > >>>>> John > >>>>> > >>>>> > >>>>> > >>>>> > >>>>> > >>>> > >>> > >> > > > > > > End of casper Digest, Vol 29, Issue 10 > ************************************** ------- End of Original Message -------
