Hi, Thought I would pass on my findings in case anyone else has the same problems.
It seems that input buses larger than 32 bits are only an issue in Verilog black boxes. VHDL boxes describing the same systems don't seem to have any problems. Creating a VHDL wrapper for my Verilog code and black boxing that also seemed to solve the problem. All mighty suspicious, but semi-solved, at least. Cheers, Jack On Mon, Apr 26, 2010 at 8:20 PM, Jack Hickish <jackhick...@googlemail.com>wrote: > Hi all, > > I'm experimenting with some black boxed state machines to simplify some of > the control logic in my designs. I thought I had it sussed, until I tried a > black box with a 64 bit wide input bus. The HDL seems unable to see the top > 32 bits of the input, and simulink refuses to recognise any of the black box > outputs which use them. > > After a bit of experimentation with a simple verilog multiplexer, it would > seem that any input buses over 32 bits don't simulate properly. (Outputs > over 32 bits don't seem to have this problem). > > I'm currently simulating within Simulink with the ISE simulator (I don't > yet have a ModelSim licence), but wondered if anyone had ever come across > this problem before...? > > Thanks folk, > > Jack >
