Hi All. Just a few comments on bus performance.
The processor bus is 16 bits at 66 MHz (or 83), so the theoretical maximum is 133 MB/s. There are 3 cycles bus overhead per transaction (for registering etc in FPGA) and an extra two or so for for accessing the register/bram. So that is roughly a bus efficiency of 1/5, so that puts the max at around 27MB/s. Incidentally, this could be improved to close to 100% by implementing a bursting/DMA scheme (this would affect BRAM access only). This will require a little work and would use the other FPGA/PPC chip select. Beyond this there are perhaps one or two cycles overhead for CPU access. So from borph you should be getting around 20 MB/s. Currently, the processor manages to program the FPGA, transferring 5MB, in around 100ms (50MB/s). Although this isn't quite a fair comparison, it gives an idea as to what speeds should be expected when accessing brams. Cheers, David
