I think it might be appropriate to look a little closer at SPEAD before jumping to conclusions.
SPEAD is a self-describing, data-streaming protocol. It has very little in the way of flow management because it is meant to sit on top of other communications layers (e.g. TCP/UDP/files/unix pipes/MPI). It is probably compatible with UDT. What SPEAD provides is the ability to interleave information from multiple sources and to synchronize that information across a distributed system. It also serializes data into a binary format that encodes information about dimensionality and data type, and reconstructs data from that binary format. This serialization is cheap, has low overhead (yet is very flexible), and is straight-forward to implement on an FPGA or CPU. That said, current FPGA SPEAD implementations are not full, parametrized implementations--they directly write the binary data that corresponds to the information they stream in a specific application. If you want to implement SPEAD on an FPGA for your application, you will also need to write this binary format directly. Fortunately, it's a straight-forward format, and it is described on the casper wiki. On Mon, Nov 29, 2010 at 8:56 AM, Jouko Ritakari <[email protected]> wrote: > Hi all, > > Had to look the spead protocol up, found some viewgraphs. > > IMHO, there were two warning signs: TCP header and small number of header > bytes. A rate-based protocol like UDT might be more appropriate. > And I have seen so many times what happens when people try to save a few > bytes out of 1500 or 9000 byte packets. It is not a nice sight. > > For your information, the hot topic nowadays is continent-wide distributed > filesystems. There are about five groups of universities competing each > year, U of Chicago has won three of the last challenges, U of Indiana the > fourth. I think the limit nowadays has been about 120 Gbps. That is not a > typo. > > We have also Jan Wagner's udtfs, a userspace udt-based filesystem. Might be > possible too put it on silicon. The Roach board is quite nice for all of > these things, offload the complicated things to the powerpc and use the > Xilinx for raw transport. > > Best regards, > Jouko > > > "Life is pretty simple: You do some stuff. Most fails. Some works. You do > more of what works. If it works big, others quickly copy it. Then you do > something else. The trick is to do something else." > > > On Mon, 29 Nov 2010, John Ford wrote: > >> Hi all. >> >> Do any of you have any xilinx designs that implement SPEAD protocol >> packets over 10 GbE? >> >> John >> >> >> >> > > -- Aaron Parsons 510-406-4322 (cell) Campbell Hall 523, UCB
