hi jonathan,
some ideas for your correlator:
1)
300 MHz is a good target, especially for V6.
suraj has shown how to achieve 375 MHz for V5
by using floor planning and auto-placing.
suraj or i can send you his draft paper on this if you'd like.
2)
you might want to consider FFX instead of FX:
eg: digitizing your 9 GHz band and using a PFB to break it up into eight
sub-bands
of 1.25 GHz each, and then sending the sub-bands into eight 1.25 GHz
FX correlators. this will simplify your switch requirements and each
correlator
now has only 4K channels, which is better suited for cornering turn in a
roach II.
3)
also, be sure to use billy's latest FFT, (recently checked in),
which moves all the adders and multipliers into DSP48's makes routing
easier.
you should also consider bit growth FFT's and PFB's, which start
out with the 4 or 5 or 8 bits from your ADC, and add bits gradually
as you move the frequency domain. dave mcmahon and hong chen
have done work on this.
best wishes,
dan
On 12/23/2010 1:47 PM, Jonathan Weintroub wrote:
Hi CASPERites,
Here's a somewhat fluffy RFI which I hope might start a little thought
and/or discussion over the season (acknowledging that not all in the
global collaboration celebrate the traditional Western winter holidays):
At SMA we are looking into the use of CASPER methods to build a ultra
wideband high spectral resolution correlator. Typical specs are, say,
18 GHz bandwidth with roughly 300 KHz spectral resolution, by two
polarizations, full Stokes. We are considering using a standard
CASPER packetized FX architecture (FX much better for high res than
XF), but in the relatively unexplored "small number of antennas, wide
bandwidth" regime. If the entire 18 GHz were eaten by one ADC, this
would require a sample rate of 40 Gsps and 64 kpoint PFB. Perhaps
more reasonable would be two 9 GHz BW blocks and a 32 k PFB sampled at
about 20 Gsps, or three 6 GHz / 16 or 32 k PFB / 14 Gsps.
To start we are looking closely at the FPGA resource utilization of
large PFBs. Something that probably is common knowledge amongst those
experienced in FX correlator design is that the demux factor drives
the utilization much faster than the size of the PFB. In that sense
bandwidth is far more expensive than spectral resolution. We've put
some effort into accurately quantifying the utilization, at least as
far as multipliers and adders are concerned, and are expanding this
analysis to block ram and other resources. And demux factor is
typically radix 2, so it is very much quantized.
For example at 20 Gsps one might consider a demux factor of 128
resulting in an FPGA clock rate of 156 MHz, which is quite comfortable
for the FPGA. Alternatively a demux factor of 64 with corresponding
FPGA clock of twice that, or over 300 MHz. Traditionally a rather
uncomfortable regime for CASPER (we're unusual, I believe, in running
iBOBs at 256 MHz for the VLBI phased array). The trouble is our
analysis shows that the difference between these two demux setting in
the size of PFB one can fit in a Virtex 6 is really quite large, and
128 definitely won't allow us to do what we need to do.
So we are increasingly highly motivated to run the FPGAs faster
still. Just a 20% increment from the 256 MHz which we currently view
as a practical upper limit allows us to cross a clock rate threshold
which then enables a factor of two decrease in demux factor, and
consequent even larger increment in the realizable PFB size.
Which is just a long winded way of asking if there are any others in
the collaboration motivated to run the FPGAs faster, and whether any
tricks can be shared? In particular, does the CASPER toolflow support
multiple clock domains? Our understanding is not yet, but that's based
on incomplete information. We know that there exists Virtex 5 (?) IP
FFT cores which supposably run at greater than 500 MHz rates, using
the enhanced interconnect between DSP slices.
While on this topic of high demux factors, the tool flow largely
chokes on demux factors of 32 or greater. Any tips here would also be
appreciated.
If anyone can cast light on this general topic and related concerns it
would be very much appreciated.
Jonathan Weintroub
SAO
