hi paul, i think most of the spurs seen in hong chen's memo will go away if one injects a small bit of noise (a few LSB's) and integrates for a while. the spurs are mostly due to 8 bit quantization of a sine wave (a stair case representation of a sine wave). when one adds a bit of noise, the quantization spurs will largely go away, and you'll be left with spurs due to interleaving, which can be quite a bit smaller than the quantization spurs. although as robert jarnot points out, depending on the ADC used, it might be hard to minimize interleaving spurs at all frequencies. best wishes, dan On 02/01/2011 10:41 PM, Hong Chen wrote:
Hello Paul, According to the datasheet, the adjustment steps are really small: 0.25LSB for offset adjustment, 0.005dB for gain adjustment and 4ps for phase adjustment. This resolution is very fine for the data we were dealing with (~100MHz, 8 bits), so theoretically we should get close to a perfect result, which the achieved one cannot even compare with. The reason why we can't achieve the predicted result seems to be beyond the interleaving issue, and currently my best guess is the existence of harmonic frequencies. When I look at the raw data directly (from a single ADC, with ~10MHz input signal frequency) and compare it with the 8-bit simulated data generated by matlab, I can see very obvious difference, the actual curve is rougher for some reason(attached graphs). It appears to be very difficult to do the perfect interleaving adjustment or to calculate the gain/phase when the other interfering factors are strong. Thank you for your question. I'm sorry I don't really know what "features of the ADCs" are limiting the performance. Best, Hong On Sat, Jan 29, 2011 at 7:20 AM, Paul Demorest <[email protected] <mailto:[email protected]>> wrote: Hi Hong and Mark, Thanks for writing this memo! This topic is important for our pulsar instruments. I was wondering if you know what the limiting factor is in how good the adjustment can be. For example, given the available resolution of the gain/phase adjustments there should be a 'theoretical best' performance. How close is your adjustment to achieving that? Are there any other features of the ADCs that might limit the performance? -Paul On Fri, 28 Jan 2011, Hong Chen wrote: Dear Casperites, Mark and I have finished a memo on the external adjustment for Atmel/e2v interleaved ADC's and it is item 40<http://casper.berkeley.edu/wiki/images/7/7f/Atmel_iadc_external_adjust.pdf>in Casper wiki's memos section. This memo investigates the interleaving issue on the e2v 1Gsps iADC board and implements python code to adjust the iadc gain, offset and delay by adjusting the control registers through the software interface. The result shows it is able to reduce the interleaving error by about 60%~85%. Your questions and comments will be appreciated. Thanks, Hong Chen
-- Dan Werthimer Space Sciences Lab and Berkeley Wireless Research Center University of Calfornia, Berkeley
