If offsets change with clock level, is that not an indication of clock
getting
into the analog input? If so, it is probably a combination of a little
bit on
the ADC chip itself and some from the board layout, which in principle
could be reduced (but what a pain to figure out just what to do!).
Regarding interleaving spurs, what happens if one adjusts the interleaving
for minimal spurs at HF? Do they then get worse at LF?
Dana Whitlow
Arecibo Observatory
On 2/2/2011 1:32 PM, Robert F. Jarnot wrote:
Hong, Paul, Francois,
We (at JPL) have spent a fair amount of time in the past
struggling with interleaving the e2v AT84AD001B (iADC/iBOB
combination). At the highest sample rates (Glenn Jones kurtosis
spectrometer for example) we find that matching with low frequency
signals as Hong described works very well. With high frequency
signals however the results are quite different, and less
encouraging. We find that matching ADC characteristics with low
frequency signals does not necessarily lead to good results with high
frequency signals. This is supported by some of the statements in the
ADC FAQs at the e2v web site. Furthermore, we have seen some other
unexpected behavior, such as offsets changing with the amplitude of
the ADC clock signal (even within the range specified by the data
sheet). At lower sample rates the AT84AD001B behaves much better, and
I suspect that is why there is now an AT84AD001C.
Our experience with interleaving the ADC083000 at 3 Gsps has been
very good in comparison.
Robert Jarnot
Message: 2
Date: Tue, 1 Feb 2011 22:41:14 -0800
From: Hong Chen<[email protected]>
Subject: Re: [casper] new memo - external adjustment for Atmel/e2v
interleaved ADC's
To: Paul Demorest<[email protected]>
Cc: CASPER Lists<[email protected]>
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hello Paul,
According to the datasheet, the adjustment steps are really small:
0.25LSB
for offset adjustment, 0.005dB for gain adjustment and 4ps for phase
adjustment. This resolution is very fine for the data we were
dealing with
(~100MHz, 8 bits), so theoretically we should get close to a perfect
result,
which the achieved one cannot even compare with.
The reason why we can't achieve the predicted result seems to be
beyond the
interleaving issue, and currently my best guess is the existence of
harmonic
frequencies. When I look at the raw data directly (from a single
ADC, with
~10MHz input signal frequency) and compare it with the 8-bit
simulated data
generated by matlab, I can see very obvious difference, the actual
curve is
rougher for some reason(attached graphs). It appears to be very
difficult to
do the perfect interleaving adjustment or to calculate the gain/phase
when
the other interfering factors are strong.
Thank you for your question. I'm sorry I don't really know what
"features of
the ADCs" are limiting the performance.
Best,
Hong
On Sat, Jan 29, 2011 at 7:20 AM, Paul Demorest<[email protected]>
wrote:
Hi Hong and Mark,
Thanks for writing this memo! This topic is important for our pulsar
instruments. I was wondering if you know what the limiting factor
is in how
good the adjustment can be. For example, given the available
resolution of
the gain/phase adjustments there should be a 'theoretical best'
performance.
How close is your adjustment to achieving that? Are there any other
features of the ADCs that might limit the performance?
-Paul
On Fri, 28 Jan 2011, Hong Chen wrote:
Dear Casperites,
Mark and I have finished a memo on the external adjustment for
Atmel/e2v
interleaved ADC's and
it is item 40<
http://casper.berkeley.edu/wiki/images/7/7f/Atmel_iadc_external_adjust.pdf
in
Casper wiki's memos section.
This memo investigates the interleaving issue on the e2v 1Gsps iADC
board
and implements python code to adjust the iadc gain, offset and
delay by
adjusting the control registers through the software interface. The
result
shows it is able to reduce the interleaving error by about 60%~85%.
Your
questions and comments will be appreciated.
Thanks,
Hong Chen
End of casper Digest, Vol 39, Issue 2
*************************************
