Hi all,
Is it possible to put more than one "dram" yellow block on a single
design? I've been getting the following error when I try this even though
they have different names ("dram" and "dram1") and are on different DIMM
(1 and 3):
Format revision of project to EDK 11.4 completed
Overriding Xilinx file <dpm_init.tcl> with local file
</opt/Xilinx/11.1/ISE/data/dpm_init.tcl>
ERROR:EDK - 2 instances with the name async_dram_1!
ERROR:EDK - 2 instances with the name dram_controller_inst!
ERROR:EDK - 2 instances with the name dram_infrastructure_inst!
ERROR:EDK - 2 instances with the name opb_dram_sniffer_inst!
ERROR:EDK - GLOBAL -
/home/sean/ddc256/XPS_ROACH_base/system.mhs line 422 -
dram_ck PORT declared again!
Thanks,
Sean
