Hi all, Thanks to the responses from a previous message, all the sync timing and timing constraints are figured out in my f-engine on roach design, clocking the FPGA at 250 MHz. I had stripped my larger design to test the data flow along a minimum of logic, which means I only left the PFB chain for 2 antennas off one ADC. The Simulink simulation runs all the way through and the data looks reasonable at every stage.
Reducing for testing meant that I had eliminated the complex logic used to change the delays that take into account the changing baseline lengths throughout the observing day. I wanted to test that the coarse_delay block would run off the ADC configuration, so I tested a very simple implementation of that logic in a separate mdl file, and everything ran great as well. However, when I combine the two parts (linking the coarse_delay to the pfb_fir_real block, the simulation fails at the 163rd clock. Specifically, one single convert_of block in the twiddle block deep in the fft_wideband_real gets an indeterminate value, and various plots from scopes don't show anything wrong other than the data flow just stopping. I've worked on this for a while now and I am now seeking any advice the group may have. For completeness, I have uploaded the mdl file for this stripped down design at http://dl.dropbox.com/u/3531421/fonroach_parts.mdl and the output of the sysgen error log is --------------------------------- Version Log ---------------------------------- Version Path System Generator 10.1.3.1386 C:/Xilinx/10.1/DSP_Tools/common/bin/../../sysgen AccelDSP 10.1.3.1386 C:/Xilinx/10.1/DSP_Tools/AccelDSP Matlab 7.5.0.342 (R2007b) C:/MATLAB/R2007b ISE 10.1.03i C:/Xilinx/10.1/ISE -------------------------------------------------------------------------------- Summary of Errors: Error 0001: Bool type output port y gets indeterminate value. Block: 'fonroach_parts/fft_wideband_real1/fft_biplex_real_4x0/biplex_core/fft_stage_1/butterfly_direct/convert_of4/slice2' -------------------------------------------------------------------------------- Error 0001: Reported by: 'fonroach_parts/fft_wideband_real1/fft_biplex_real_4x0/biplex_core/fft_stage_1/butterfly_direct/convert_of4/slice2' Details: Bool type output port y gets indeterminate value. -------------------------------------------------------------------------------- Thank you very much, Samuel Tun
