Hi,

Before doing some board surgery and mistakenly swapping out
the wrong part could I get confirmation
that I have the QDR number to reference designator mapping
correct ?

From a recently used, but  not the FPGA self test, design
directory ./implementation/system.ucf I find
  NET "qdr0_d<0>"      IOSTANDARD = HSTL_I     | LOC = R11;
  NET "qdr0_d<1>"      IOSTANDARD = HSTL_I     | LOC = T11;
  ..
  NET "qdr1_d<0>"      IOSTANDARD = HSTL_I     | LOC = G21;
  NET "qdr1_d<1>"      IOSTANDARD = HSTL_I     | LOC = F21;
  ..

and the revision 1.03 of the schematics has
  FPGA pin R11 as net qdr2_by0_1_d0 which goes to U63 pin p10.
And
  FPGA pin G21 as net qdr2_by2_3_d0 which goes to U17 pin p10.

This matches the notes from http://casper.berkeley.edu/wiki/ROACH_Bringup
That the  FPGA test design maps
  # QDRII+ SRAM 0 to U63
  # QDRII+ SRAM 1 to U17

So it seems to all match to me.
What says you ?

Thanks,

Matt

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