Hi, I'm getting into a small mess with tutorial 2. For simulations, I understand it is necessary to limit the data rate if we want to use ten_Gbe_V2 blocks and 200MHz for the fpga clock. For this reason it is used some kind of PWM signal (50 over 200 fpga clocks), isn't it?
However, I don't know why this value would limit the hardware data rate to (50/(8/10)*156.25)= 4Gbps. Firstly, I get 0.4. Secondly, I know '8/10' is due to the codification and '156.25' is due to Xtal, but.. what about '50'? Is it due to the PWM signal? Appart from that, in the tut2.py, the values of the PWM signal are 128 over 16383, why are these specific values been chosen? Can I change them? Thanks a lot, Miguel. -- Miguel <[email protected]>
