[casper] clock signals

[Jesús García]

 Hi Rick,
I think you are wrong, because with that block I ran a design using a 
sampling rate of 600MHz.
Moreover my ADC board is:
ADC2x1000-8 (2005 - present | dual 1GSa/sec)
Dual 8-bit, 1000Msps (or single 8-bit 2000Msps), Atmel/e2v AT84AD001B ADC
So 1200 MHz in interleave mode is also possible, isn't it?
Jesús