Hi Dan,
What I’m doing right now is not specifically targeted at the Roach board or even Xilinx FPGAs. However, I only have access to a Roach board that’s why I’m trying to use it to do some hardware testing. For the moment I don’t have the Casper tools and what goes with them but If I needed to do more than just verification It would certainly make things easier if I wrapped my design in a bloc and used the Simulink-Casper design flow. Cheers, Aziz. On Thu, Jul 7, 2011 at 7:55 PM, Dan Werthimer <[email protected]> wrote: > ** > > > hi aziz, > > can you use the standard casper libraries and tools? > > if you can use the standard libraries and tools, > then you will be able to share your designs with > the casper community as well as use the casper libraries > and open source instrument designs. > you'll also be able to get a lot of help from the community > as well as be able to help others if you can use the same tools > and libraries. > > if you want to program in VHDL or Verilog, i suggest you > put your code inside a simulink block (or blocks); then > you can interface to BORPH, use the standard linux distribution, > use the ADC and other interfaces, and be compatible with > the casper community. > > best wishes, > > dan > > > > On 7/7/2011 11:45 AM, A.S. Aziz wrote: > > Hi, > > Thanks for the link, I got the UCF file which has all the FPGA pin > connections in it so that is very good. > > Now I just need to find how to program the FPGA. One option to create a BOF > file using mkbof, I tried that but I got an error. I think its because I do > not have a valid core_info.tab file. I just used the one from ROACH_BASE. > > Can you explain how to manually make a core_info.tab file? If I just need > to modify the existing one can you explain what should I modify and how? > > If I succeed in making a BOF file I still need to know what to have on the > FPGA side in order to talk to the powerpc the way it is supposed to be in > BORPH. Is this explained somewhere? > > > > The other possible option is to write a C code to configure the FPGA > directly from the bitstream file and choose my own communication protocol > between the PPC and the FPGA (which would be an ideal solution for me). > > > Does BORPH provide an API for that? > > > > Thanks for your reply, > > > > Aziz > > > On Thu, Jul 7, 2011 at 8:50 AM, David George <[email protected]>wrote: > >> Hi Aziz. >> >> > I want to use a Roach board (one with virtex5 FPGA) to test some VHDL >> > designs and I’m not using Simulink, matlab, XPS . To do so I need to >> know >> >> You could start with this project: >> >> https://casper.berkeley.edu/svn/trunk/roach/gw/roach_bsp/ >> >> It is a verilog project we use to test the ROACH boards. It has a >> make-based build. You will need standard GNU tools, iverilog and >> Xilinx ISE installed. This is best compiled under Linux, but can be >> compiled in windows with cygwin. This project doesn't have that much >> polish to it. >> >> It may be better to use the XPS (EDK) project as your starting point. >> casper git: xps_lib/XPS/ROACH_base >> You should be able to use the EDK gui to create your design. >> >> > how to create a BORPH compatible interface between the FPGA and the >> PowerPC. >> As for a borph compatible file. Your compile should produce a .bin >> file which you use combine with a core_info.tab file with the mkbof >> utility. There should be plenty of coreinfo.tab files around to work >> out the format. Refer to the MSGGE build scripts for how to run mkbof: >> casper git: xps_library/ >> >> > What I’m looking for is information regarding the connection between the >> > FPGA and the PPC such as pins, communications protocol …and how to >> manually >> The PPC datasheet has tons of info on that interface (refer to the >> external bus controller section): >> >> http://myapm.apm.com/MyAMCC/retrieveDocument/PowerPC/440EPx/PPC440EPx_440GRx_UM2018.pdf >> Also, the EDK and ISE projects mentioned earlier have HDL code which >> uses this interface. >> >> > Any low level technical document describing the architecture of the >> ROACH >> > and its OS would be very appreciated. I would also appreciate any >> example. >> The best (and only existing) low-level documentation is in the >> existing code. The schematics are available on the wiki, which should >> help out. >> >> Regards, >> David >> > > >
