Hi All,

I don't have our own results in a handy packaged format, but this correlates
well with what we saw.  If the 533 MHz is fundamental, it is pure PowerPC -
the clock is generated on chip from a lower frequency reference.

Regards,
Francois

On Tue, Sep 6, 2011 at 10:29 PM, John Ford <[email protected]> wrote:

> > John,
> > It's interesting that there is almost no evidence of the 500 MHz ADC
> > clock,
> > except perhaps the 2000 MHz tone. I guess that means the ADC clock
> > transmission lines are well terminated and not radiating. Most of the
> > lines
> > look like they are related to the PPC (multiples of 33 MHz) and the 100
> > MHz
> > system clock.
>
> You're right that most of this is due to the PPC and ancillary circuits.
> I expect that it's because the FPGA is not loaded.  The line from the
> clock to the ADCs is very short.  I am going to test it again later with
> the FPGA running a spectrometer bof, and all the xaui cables connected and
> passing data around.
>
> For now, this is enough to tell me that we need to be thinking ahead to
> packaging VEGAS.
>
> John
>
> > Glenn
> >
> > On Tue, Sep 6, 2011 at 1:14 PM, John Ford <[email protected]> wrote:
> >
> >> Hi all.
> >>
> >> We tested a ROACH and and 2 ADC boards (3 GS/s boards) in our anechoic
> >> chamber to get a feel for the emissions to expect from the new
> >> spectrometer being designed.  The ADC clock was running at 500 MHz.
> >>
> >> The results of the test are attached.  In summary, to use these at our
> >> site, we will have to have a supplementary shielded enclosure in
> >> addition
> >> to our shielded equipment room.
> >>
> >> Thanks to Carla Beaudet at NRAO for the testing.
> >>
> >> (If anyone has anything they'd like us to test in the chamber, let me
> >> know.)
> >>
> >> John
> >
>
>
>
>


-- 

Francois Kapp

Sub-system Manager
Digital Back End
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