Hi Miguel
With regards to your second problem:
I've had a similar problem before, where I would write registers in
KATCP, but when I read them back, they were all zeroes. I "fixed" this
by deleting ALL the temporary and output files that Simulink generated,
and recompiling the design from scratch.
I don't know about your first problem though.
Simon
On 21/09/2011 02:11, Miguel wrote:
Hi all,
I've made a model with the ACD and 10gb core. The simulation seems to be
ok and I have the bof file too but when I program the fpga I get two
problems:
1.- "There is no cable plugged into port 0" (but yes there is).
Surprinsingly this problem only happens sometimes. It is not because of
the cable. I have changed it and if I run other model (like tut1 or
tut2) the cable works fine. So, it's about my model but i don't know
what I'm doing wrong. Has somebody found this problem before or somebody
has any idea why could it be due to?
2.- When I try to read some software registers with katcp or borph it
seems they aren't wrote (but in simulations they are). I have copied the
structure from tut2 model. I'm talking about a software register where I
store the number of packets delivered to 10gbe core.
Thanks a lot.
Miguel.
