Thanks Jason- that worked. Never thought to actually follow the
recommendation. Actually, I did, but found the Simulinl "Assertion"
block rather than the Xilinx "Assert" block, and gave up.
Rick
On 1/22/2012 10:49 PM, Jason Manley wrote:
It sounds like it's having problems figuring out what bitwidths or sample rates
to use. Have you tried adding an assert block like they suggest and explicitly
setting the data type?
If there's a line present between two non-Xilinx or non-Simulink primitives (or
to a Xilinx primitive from an unknown source), then it won't be able to
automatically propagate datatypes and so you should just set it explicitly. One
way to do this is using an assert block.
Jason
On 21 Jan 2012, at 01:42, rick raffanti wrote:
Hi Casperites,
I have a model which I've made some pretty small changes to and now I get some errors
which I'm not familiar with. They seem to have to do with the simulation model, which
I'm not even using, so I wonder if I can just switch all that off somehow. The errors
have to do with sample rates and data types, eg, "Rates and types have converged
for the feedbackpath through these blocks. However, the solution contains unknowns.
Could not establish types for the blocks listed at the end of this message. You may need
to add an Assert block to instruct the system how to resolve rates and types" Then
it lists an inverter and a register.
I've included a new "black box" which wraps some Verilog. I've done this
befoer successfully (elsewhere in this design, in fact).
Anybody have any ideas?
Thanks,
Rick
