Hi Devon, Just had a quick look at your mdl file. Looks like you're holding the qdr_vacc write enable signal high - I'm pretty sure the block only lets you read out an accumulation on the cycles when the qdr_vacc input isn't valid. On the clocks when the input data is valid, the qdr read cycles are used to grab the running totals for the accumulator's add operation, and so can't be used for reading out results.
Also, you've probably checked other values, but the python script you attached sets the accumulation length to 1 - I haven't looked too hard at the vacc block, but I wouldn't be surprised if this is a special case which doesn't work. Failing any of the above helping, checking the status register inside the qdr_vacc block might help shed some light on what's going on. Good luck, Jack On 24 January 2012 02:38, Devon J Rosner <[email protected]> wrote: > Hi Casper group, > > I am a junior at MIT working with the MKI lab on the Omniscope project. > After creating some tests for the qdr_vacc block, the grad student I am > working with and myself were getting data that did not make sense. We first > made the input to the qdr_vacc a counter, but the data outputs were all 32 > bits of 1's. Later, we made a test where we could input custom lists, and > even after inputting all 0's, the output was still 32 bits of 1's per data > out. Any help with this problem would be greatly appreciated. > > Attached is the python script we used to initialize the roaches, and the > .mdl file of our design. > > Thank you, > Devon Rosner > -- > Devon Rosner > Massachusetts Institute of Technology Class of 2013 > Course VI-1 > Electrical Engineering >
