The pcore block is in the model, the names seem to be the same from the original blackboxpfb2.mdl file to its use in the testblackbox.mdl file, and the names and widths in the VHDL file seem to match the original mdl file. I tried using relative paths to the NGC and VHDL files and then absolute paths without differences in results. The reason I attached the zipped tar file to my previous email is I think there may be some other subtle error. Did you see any problem?
> I thought I stayed inside the rules. > Attached is a zipped tar file with the > blackboxpfg2.mdl and testblackbox.mdl > files of my second attempt. Also in the > tar file are the VHDL and Matlab files > generated by the procedure. Do you see > any violations? > >> A few possibilities come to mind: >> >> 1) Did you remember to add a "pcore" block to the model (see section 3.4 >> of the Black Boxing article)? >> >> 2) Have you changed the name or width of a Gateware In or Gateway Out >> block in the model that defines the netlist? If so, you might need to >> have the block box wizard regenerate the *_core_config.m file for you >> (or >> make the appropriate edits manually if you prefer). >> >> 3) Make sure that the port names and widths listed in the *_core.vhd >> file >> (in your top level directory), and in the *_core_config.m file, and in >> the >> *_core.mdl file all match. Watch out for Gateway In/Out blocks whose >> name >> is a VHDL reserved word. >> >> Hope this helps, >> Dave >> >> On Jan 30, 2012, at 5:52 PM, [email protected] wrote: >> >>> I am having trouble with my Black Boxes. >>> Compile times for my models are so long >>> that I need to use the Xilinx Black Box >>> feature. I have the article by "Optimize >>> CASPER Development by 'Black Boxing' >>> Designs" by David MacMahon November 23, >>> 2010. David's procedure seems to easily >>> build black boxes, but when I use bee_xps >>> to compile simple models that use them, I >>> get the following dreaded messages. >>> >>> ERROR:NgdBuild:604 - logical block >>> 'testblackbox_XSG_core_config/ >>> testblackbox_XSG_core_config/testblackbox_x0/ >>> my_blackboxpfb_core' with type 'blackboxpfb_core' >>> could not be resolved. A pin name misspelling can >>> cause this, a missing edif or ngc file, or the >>> misspelling of a type name. Symbol >>> 'blackboxpfb_core' is not supported in target >>> 'virtex5'. >>> >>> Making my "blackboxpfb" black box >>> created a subdirectory "blackboxpfb_core" >>> with the following contents. >>> >>> addsb_11_0_bdb276565dee6659.ngc bmg_33_9d3bf13e9a4d9a01.mif >>> blackboxpfb_core_cw.gise bmg_33_9d3bf13e9a4d9a01.ngc >>> blackboxpfb_core_cw_import.log bmg_33_9fed4de7958f9a58.mif >>> blackboxpfb_core_cw_import.tcl bmg_33_9fed4de7958f9a58.ngc >>> blackboxpfb_core_cw.ise bmg_33_a33051899a02b0df.mif >>> blackboxpfb_core_cw.sdc bmg_33_a33051899a02b0df.ngc >>> blackboxpfb_core_cw.sgp bmg_33_a38853f09a992471.mif >>> blackboxpfb_core_cw.ucf bmg_33_a38853f09a992471.ngc >>> blackboxpfb_core_cw.vhd bmg_33_a472e9469e1a55bc.mif >>> blackboxpfb_core_cw.xcf bmg_33_a472e9469e1a55bc.ngc >>> blackboxpfb_core_cw_xdb bmg_33_b433f7e31442d1b4.mif >>> blackboxpfb_core_cw.xise bmg_33_b433f7e31442d1b4.ngc >>> blackboxpfb_core.ngc bmg_33_bde0d98b7c268d95.mif >>> blackboxpfb_core.vhd bmg_33_bde0d98b7c268d95.ngc >>> blackboxpfb_core.vho bmg_33_be5a393c8320608f.mif >>> bmg_33_01dd252156a2c7b3.mif bmg_33_be5a393c8320608f.ngc >>> bmg_33_01dd252156a2c7b3.ngc bmg_33_c0ac3413361ea52b.mif >>> bmg_33_047c125a73f3c1f0.mif bmg_33_c0ac3413361ea52b.ngc >>> bmg_33_047c125a73f3c1f0.ngc bmg_33_c5560a636d03fc1c.mif >>> bmg_33_482b8d0961f68d52.mif bmg_33_c5560a636d03fc1c.ngc >>> bmg_33_482b8d0961f68d52.ngc bmg_33_d4b4989bce18e25c.mif >>> bmg_33_4ed11faae7e5e6b4.mif bmg_33_d4b4989bce18e25c.ngc >>> bmg_33_4ed11faae7e5e6b4.ngc bmg_33_dff652364d3ec538.mif >>> bmg_33_55833db8ed9147a1.mif bmg_33_dff652364d3ec538.ngc >>> bmg_33_55833db8ed9147a1.ngc bmg_33_e1a35aaacd7ca869.mif >>> bmg_33_561be7213f0e7611.mif bmg_33_e1a35aaacd7ca869.ngc >>> bmg_33_561be7213f0e7611.ngc bmg_33_e5a5cae348665945.mif >>> bmg_33_5fb1618bdd9e2378.mif bmg_33_e5a5cae348665945.ngc >>> bmg_33_5fb1618bdd9e2378.ngc bmg_33_e6871bb194f4a37b.mif >>> bmg_33_6101afd66f01b855.mif bmg_33_e6871bb194f4a37b.ngc >>> bmg_33_6101afd66f01b855.ngc bmg_33_f375f5a3a02b6146.mif >>> bmg_33_7592cf5466cc0a10.mif bmg_33_f375f5a3a02b6146.ngc >>> bmg_33_7592cf5466cc0a10.ngc cntr_11_0_64b6c809edee1e81.ngc >>> bmg_33_7a66187dde5fb2db.mif cntr_11_0_9cd1168730d276e8.ngc >>> bmg_33_7a66187dde5fb2db.ngc commandLines >>> bmg_33_7b6922b2a0594c9d.mif globals >>> bmg_33_7b6922b2a0594c9d.ngc hdlFiles >>> bmg_33_8008c267f268c930.mif isim_blackboxpfb_core.prj >>> bmg_33_8008c267f268c930.ngc name_translations >>> bmg_33_8158159440be6c26.mif SgIseProject.tcl >>> bmg_33_8158159440be6c26.ngc synopsis >>> bmg_33_845cfe1c79250673.mif synth_model >>> bmg_33_845cfe1c79250673.ngc sysgen >>> bmg_33_8478501b21bb5c0f.mif vcom.do >>> bmg_33_8478501b21bb5c0f.ngc xlpersistentdff.ngc >>> bmg_33_8a3f1db33d02b6d7.mif _xmsgs >>> bmg_33_8a3f1db33d02b6d7.ngc xst_blackboxpfb_core.prj >>> bmg_33_8e043b8dc69da1e8.mif xst_blackboxpfb_core.scr >>> bmg_33_8e043b8dc69da1e8.ngc >>> >>> My Matlab list of paths includes my >>> work directory and this subdirectory. >>> In my work directory, there is also a >>> "blackboxpfb_core.vhd" that was >>> generated by "extract_entity" in one >>> of the steps for making the black box. >>> Thus, there are two of these VHDL files, >>> one in my work directory and one in the >>> "blackboxpfb_core" subdirectory. The >>> two VHDL files differ, but were both >>> generated by the procedure given in >>> David's article. I have CASPER library >>> mlib_devel_10_1 and Xilinx 11.1 >>> software. My Matlab version is 2009a. >>> >>> What did I do wrong? >>> >>> >>> >>> >> >> >> >
