Thanks Henno and Jason, It was just this cross-mapping vs use in software that was getting me confused. Relieved to have your input.
Matt On Tue, 10 Apr 2012, Henno Kriel wrote:
Hi Jason I have checked the clocking and agree. Henno On Tue, Apr 10, 2012 at 1:06 PM, Jason Manley <[email protected]> wrote: Oops, sorry, I think I've just confused myself and mis-informed you in the process. Having checked the schematics, it seems... X1 drives MGT_REFCLK_Q1_1 and MGT_REFCLK_Q1_3 (ie ports 1 and 3) through buffer U8, both going in to FPGA. X4 drives MGT_REFCLK_Q2_0 and MGT_REFCLK_Q2_2 (ie ports 0 and 2) through buffer U26, both going in to FPGA. I can only guess that this was done to make both clocks are available to both MGTs, allowing full flexibility from software. However, in the software, only two reference clocks, xaui0_ref_clk and xaui2_ref_clk seem to be used. This maps to mgt_clk_b and mgt_clk_t, respectively. xaui0_ref_clk (mgt_clk_b) is used for ports 0 and 1 and xaui2_ref_clk (mgt_clk_t) for ports 2 and 3. You can check this in the system.mhs and xaui_infrastructure pcore. From the UCF, the top clock maps to C8/D8 (MGT_REFCLK_Q1_1) and the bottom clock to Y3/Y4 (MGT_REFCLK_Q1_3). So it looks like XTAL X1 is used for both. I'm not sure if this was the original design idea. Looking at this, we should be able to leave out X4 and U26 completely and still have a fully functioning board! It'd be nice to have someone double-check my reasoning here. I can confirm that your ordering of the ports on the back is correct according to the yellow block's port numbering. Jason On 10 Apr 2012, at 11:30, Jason Manley wrote: > Hi Matt > > I have, for ROACH-1: > > X1: > CX-0 maps to MGT bottom 0 > CX-1 maps to MGT bottom 1 > > X4: > CX-2 maps to MGT top 0 > CX-3 maps to MGT top 1 > > Jason > > > > On 07 Apr 2012, at 03:46, Matt Dexter wrote: > >> Hi, >> >> I've confused myself when I try to map CX4 port to reference >> crystal - I hope one of you can help me unconfuse me. >> >> When viewing the rear of the Roach1 board, with components on top, >> the design tools call out, I think, the CX4 ports as: >> upper left=2 upper right=1 >> lower left=3 lower right=0 >> >> What is the mapping of these ports to the two 156.25 MHz >> reference crystals X1 and X4 as shown on pages 8 and 9 of >> the schematics ? >> >> Thanks, >> Matt Dexter >> >> > Jason Manley 082 662 7726 -- Henno Kriel FPGA Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050
