Hi andrew thanks a lot for your answer. I have some more questions. - According to your answer, all the computation in order to get the time delay between signals is made by software and off line, instead of calculating that delay in the FPGA and in Real Time. So first, ¿how do you get the number of samples that the signal should be delayed in the coarse delay block? I imagine that the signals after the ADC are stored and then, for example in Matlab or Python, a kind of cross correlation in the time domain is calculated in order to get that number of samples. Please, could you confirm me this? and if it is possible could you describe which algorithm are you using?
- Once the coarse delay is corrected, we have to correct the fractional delay in the frequency domain. You say you don't need to calculate the phase difference among the different bins of the antennas because you already know the position of the source and the antennas... but could you please send me an example just to know how to get those phases... - Those phase differences are calculated at the beginning and then they don' need to be updated in the time? - How do youn choose the number of bins? - How do you calculate the fringe rotation? I have another question connected with the reference signal of 10 MHz. I am using the TIMETECH equipment that is advised in the Casper web, in order to generate a 10 MHz reference. Then all my Signal generators use this reference signal in order to generate the clock signals for the ADC, DAC...and also for the LNBs of the two antennas. The problem is that, although the two LNBs are using the same reference signal, each one has its own PLL. So I think I have a little offset between the two signals I get from the two antennas. How Casper have solved this problem? thanks in advanced, and kind regards, Jesús -----Original Message----- From: Andrew Martens <[email protected]> To: Jesús García LLedó <[email protected]> Cc: casper list <[email protected]> Date: Tue, 19 Jun 2012 15:37:27 +0200 Subject: Re: Some questions Hi Jesus I am including the CASPER list in my reply as your questions are probably shared by almost anyone developing correlators/beamformers. On Mon, 2012-06-18 at 14:57 +0200, Jesús García LLedó wrote: > Hi Andrew, > > I write you in order to speak you about a problem I am dealing with. Firstly I would like to tell you some details of my problem and I will try to avoid boring you. > > The idea is to implement an Antenna Array to receive signals from geostationary satellites. These kind of satellites can be seen a signal source fixed in the sky. > Now, to make things simpler, we only want to implement a two antenna correlator. > The signal from the Satellite arrives to each of the antennas, but as these antennas are separate in the space, we have some delay between these two signals. > So what we have to do is just to correct this delay, and them sum these two signals. Making this we would improve the Signal to Noise ratio of the resultant signal in 3dBs. > We want to make this with broadband communication signals. At least with a bandwidth of 100MHz. > > I think this is more or less the working philosophy of CASPER, so we could use some of the tools and blocks which are already implemented.To do this I also > think that with a RoACH board, a KatAdc Board and a DAC board it will be enough. > > I write you to ask you about the blocks that I would need to solve this problem. You will only need the DAC if you want to transmit. A katADC will give you two inputs, I am assuming that you have only a single polarisation per antenna? The iADC will also be fine if you don't need the variable gain and switch to ground offered by the katADC. > I think in CASPER, time delay between the signals is measured and corrected in the frequency domain. It is more accurate to say that our correlators are FX correlators so we try to do things in the frequency domain where possible. However, this could be done in the time-domain, we just don't have as much support for it. There are plans at Manchester to develop a programmable group delay FIR filter block so that fractional (less than one ADC sample) delay can be done in the time domain. > I suppose that the PFB + FFT block divides the spectrum of the signal into several bins, then for each bin the phase difference from the two antenna signals is measured > (but I don't know with wich block...) and afterwards I guess that phase difference is corrected, the two signals are summed and then a synthesis filter (the inverse of the > PFB + FFT block) is necessary to return to the time domain.... The process in our systems is as follows; 1. The signal is sampled by the ADC 2. The signal can be delayed by multiples of one sample in a block called a 'coarse delay' block (delay_wideband_prog in Delays subsection of library). This allows most of the delay to be removed. 3. The PFB/FFT divides the signal into bins. 4. The final fraction of delay can be removed using complex multiplication to rotate the phase of the data in the FFT bins. This is done in a block called the 'fine delay' block. I can send the one we use to you as it is not yet in the library. If you are not using baseband signals you will need to do fringe stopping at this point too. 5. We add the signals from different antennas and transmit the the result. Note a few things; 1. We don't go back to the 'time-domain' i.e no synthesis filter. 2. We don't measure the phase difference in the FPGA. We use software to calculate the delays in advance given that we know the position of the antennas and source. Attached is an image showing the data flow in our system to help explain. Regards Andrew
