Hi Luis I am copying to the casper list as others may find this useful.
> I wonder where are the en0/1 and atten0/1 signals for the katADC? I > tried to find it in the Verilog code (e.g. gain_set.v in I2C controller > pacore) or schematics, and I can not see any reference. The only thing > that I can see is gain_value_latch divided in "half" for I and Q channels. I would advise looking under the mask at the katadc yellow block. You will see that en0, atten0, en1, and atten1 are combined to form one value (*_katadc_gain_value) that is passed on to the IIC controller that writes these values out if needed. The FPGA logic is set up to automatically load any value on these inputs on configuration and then to reload if any values change. > The question is, how to use gain_value? Is something like, atten0 = > gain_value[5:0] and atten1 = gain_value[12:7] (see gain_set.v in the > libraries)? You will see the mapping in the katADC yellow block. Basically; gain_value[5:0] = inverse ( atten0 ) gain_value[6] = en0 gain_value[12:7] = inverse ( atten1 ) gain_value[13] = en1 > What are gain_value[6] and gain_value[13]? Are these the > control bits for the 50Ohm coupling (CH1_TERM and CH2_TERM in the > schematics)? Yes. There is an RF mux that can terminate the ADC input into 50Ohm (en? = 0) or connect it to the input RF (en? = 1). We use these to protect our ADCs (if the ADC is over-ranging for a long period of time we terminate the input). > What about the gain_load (single bit) input to the block? That triggers the load of a value via the I2C bus as explained above. Hope this helps Regards Andrew
