Hi Jay, Unfortunately, the secret sauce of the Shared BRAM yellow block is that it uses the dual-port BRAM under the hood; one port goes to the FPGA fabric, and the other goes to the processor bus.
The single-port bram block under the mask is just there to provide a simulation model, and doesn't actually get implemented. So to do a dual-ported shared BRAM, you'd probably need to add arbitration on one of the ports to share it between the fabric and processor so that it's architecturally a tri-ported BRAM o_o On 6/29/2012 3:56 PM, Jay Brady wrote:
I'm working on a project that currently uses a dual-port BRAM (generated from Coregen) in a VHDL black-box. I would like to port the address/data signals outside of the box and use a shared BRAM yellow block so I can read and write from ipython, but sadly the yellow block is only single ported. Is there a dual-port shared BRAM, or would it be possible to make one myself? If the latter, how would I go about it? I was tempted to go under the mask of the yellow block and just replace the Xilinx single-port bram block with the Xilinx dual-port block, but I don't know if there are any configuration files or vhdl that would need to be updated along with it. Any help/documentation on the process would be great. Thanks, Jay
