Hi, We're working on some calibration logic for a new ADC for the ROACH II. The logic needs an always available clock, so we're trying to use sys_clk. Using ROACH II, when we have something like this in our system.mhs file:
BEGIN calibration_block ... PORT clk = sys_clk ... It compiles OK, but the logic then acts as though clk is connected to a ~ 500 MHz clock. (We have the block outputting clk/4 to a gpio, and it is toggling at 125 MHz) We then tried using sys_clk2x to see if the gpio output speed tracks the clk input. We found that it was still toggling at 125 MHz. Our test simulink design is clocked from sys_clk, and est_brd_clk returns ~ 100 as expected. Our VHDL simulates perfectly in ISE, so I'm not sure what the issue might be. Any suggestions? Thanks, Glenn and Jama
